Sharp DX-SX1 (serv.man2) Service Manual ▷ View online
DX-SX1H
– 53 –
IC606 RH-iX1473GEZZ: Digital Servo (IX1473GE) (1/3)
1
VSS
—
Digital ground terminal
2
BCK
Output
Bit clock (1.4122 MHz) output terminal
3
AOUT
Output
Audio data output terminal
4
DOUT
Output
Digital-out output terminal
5*
MBOV
Output
When buffer memory over signal output terminal is over: "H"
6
IPF
Output
When AOUT output of correction flag output terminal shows the correction impossible
symbol: "H"
symbol: "H"
7*
SBOK
Output
When CRCC judgment result output terminal of sub-code Q data shows OK: "H"
8*
CLCK
Input/Output
Can be selected by using the clock output/input terminal command bit for reading
sub-code P-W data.
sub-code P-W data.
9
VDD
—
Digital + power terminal
10
VSS
—
Digital ground terminal
11*
DATA
Output
Sub-code P-W data output terminal
12*
SFSY
Output
Reproductive frame sync signal output terminal
13
SBSY
Output
When sub-code sync of sub-code block sync output terminal is detected: "H" at the
position of SI
position of SI
14*
SPCK
Output
Output terminal of the clock (176.4 kHz) for reading processor status signals
15*
SPDA
Output
Processor status signal output terminal
16*
COFS
Output
Correction frame clock (7.35 kHz) output terminal
17*
MDNIT
Output
Can monitor DSP internal flag and PLL clock by using microcomputer commands of
LSI internal signal monitor terminal
LSI internal signal monitor terminal
18
VDD
—
Digital + power terminal
19
TESIO0
Input
Test input/output terminal. Normally fixed at "L".
20
P2VREF
—
PLL special 2VREF terminal
21*
SPDO
Output
VCO center frequency shift terminal
22*
PDOS
Output
Phase error (between EFM and PLCK) signal output terminal
(to be used in case of 8-time speed operation)
(to be used in case of 8-time speed operation)
23
PDO
Output
Output terminal for phase error signal between EFM signal and PLCK signal
24*
TMAXS
Output
TMAX detection result output terminal. Selected by command bit TMPS.
25
TMAX
Output
26
LPFN
Input
Inversion input terminal of amplifier for low-pass filter
27
LPFO
Output
Output terminal of amplifier for low-pass filter
28
PVREF
—
VREF terminal for PLL system
29
VCOREF
Input
VCO center frequency reference level terminal. Normally fixed at "PVREF".
30
VCOF
Output
Filter terminal for VCO
31
AVSS
—
Analog system ground terminal
32
SLCO
Output
Output terminal of DAC for generating data slice level
33
RFI
Input
RF signal input terminal
34
AVDD
—
Analog power terminal
35
RFCT
Input
RFRP signal center level input terminal
36
REZI
Input
Input terminal for RFRP zero-cross
37
RFRP
Input
RF ripple signal input terminal
38
FEI
Input
Focus error signal input terminal
39
SBAD
Input
Sub-beam adding signal input terminal
40
TSIN
Input
Test input terminal. Normally fixed at "Vref".
41
TEI
Input
Tracking error signal input terminal (Input when tracking servo is ON.)
42
TEZI
Input
Input terminal for tracking error zero cross
43
FOO
Output
Focus equalizer output terminal
Pin No.
Terminal
Name
Input/Output
Function
Remarks
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
TMAX Detection result
TMAX Output
Longer than the specified frequency
"P2VEFF"
Shorter than the specified frequency
"VSS"
Within the specified frequency
"HiZ"
DX-SX1H
– 54 –
IC606 RH-iX1473GEZZ: Digital Servo (IX1473GE) (2/3)
44
TRO
Output
Tracking equalizer output terminal
45
VREF
—
Analog reference power terminal
46*
RFGC
Output
Outputs 3-pole PWM signal of RF amplitude adjusting signal output terminal.
(PWM carrier = 88.2 kHz)
(PWM carrier = 88.2 kHz)
47
TEBC
Output
Outputs 3-pole PWM signal of tracking balance control signal output terminal.
(PWM carrier = 88.2 kHz)
(PWM carrier = 88.2 kHz)
48
FMO
Output
Outputs 3-pole PWM signal of feed equalizer output terminal.
(PWM carrier = 88.2 kHz)
(PWM carrier = 88.2 kHz)
49*
FVO
Output
Outputs speed error signal or 3-pole PWM signal of feed search EQ output terminal.
(PWM carrier = 88.2 kHz)
(PWM carrier = 88.2 kHz)
50
DMO
Output
To output PWM signals of 3 poles of disc equalizer output terminal.
(PWM carrier = DPS 88.2 kHz, synchronizing with PXO)
(PWM carrier = DPS 88.2 kHz, synchronizing with PXO)
51
2VREF
—
Reference power terminal
52
SEL
Output
Laser diode control signal
53
FLGA
Output
FLG-A output terminal
54
FLGB
Output
FLG-B output terminal
55*
FLGC
Output
FLG-C output terminal
56
FLGD
Output
FLG-D output terminal
57
VDD
—
Power terminal
58
VSS
—
Connected to GND.
59-62
IO0-IO3
Input/Output
General-purpose I/O port
(60*)
Can be switched to input/output port possible according to commands.
In case of input port: can read terminal condition (H/L) by read commands possible.
In case of output port: can control terminal condition (H/L/HiZ) by commands possible.
In case of input port: can read terminal condition (H/L) by read commands possible.
In case of output port: can control terminal condition (H/L/HiZ) by commands possible.
63
/DMOUT
Input
Terminal for setting the mode outputting feed equalizer binary PWM from IO0 and 1
terminals and disc equalizer binary PWM from IO2 and 3 terminals. "L": active.
terminals and disc equalizer binary PWM from IO2 and 3 terminals. "L": active.
64
/CKSE
—
X'tal select terminal. In case of 16.9344MHz: "H"; in case of 33.8688 MHz: "L"
65*
/DACT
—
Test terminal
66
TESIN
Input
Test input terminal
67
TESIO1
Input/Output
Test input/output terminal
68
VSS
—
Digital ground terminal
69
PXI
Input
DSP system clock oscillation circuit input terminal
70
PXO
Output
DSP system clock oscillation circuit output terminal
71
VDD
—
Digital + power terminal
72
XVSS
—
Ground terminal for system clock oscillation circuit
73
XI
Input
System clock oscillation circuit input terminal
74*
XO
Output
System clock oscillation circuit output terminal
75
XVDD
—
+ power terminal for system clock oscillation circuit
76
DVDD
—
D/A conversion section power terminal
77*
RO
Output
Channel R data normal rotation output terminal
78
DVSS
—
D/A conversion section analog ground terminal
79
DVR
—
D/A conversion section reference voltage terminal
80*
LO
Output
Channel L data normal rotation output terminal
81
DVDD
—
D/A conversion section power terminal
82
TEST1
Input
Test terminal
Pull-up
Normally open
resistor built in
83
TEST2
Input
Test terminal
Pull-up
Normally open
resistor built in
84
TEST3
Input
Test terminal
Pull-up
Normally open
resistor built in
85
BUS0
Input/Output
Data input/output terminal for microcomputer interface
Schmitt input
86
BUS1
Input/Output
CMOS port
87
BUS2
Input/Output
88
BUS3
Input/Output
Pin No.
Terminal
Name
Input/Output
Function
Remarks
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
DX-SX1H
– 55 –
IC606 RH-iX1473GEZZ: Digital Servo (IX1473GE) (3/3)
89
VDD
—
Digital + power terminal
90
VSS
—
Digital ground terminal
91
BUCK
Input
Clock input terminal for microcomputer interface
Schmitt input
92
/CCE
Input
Chip enable signal input terminal for microcomputer interface
Schmitt input
"L": BUS0 to 3 are active.
93
TEST4
Input
Test terminal
Pull-up
Normally open
resistor built in
94
/TSMOD
Input
Local test mode select terminal
Pull-up
resistor built in
resistor built in
95
/RST
Input
Reset signal input terminal
Pull-up
"L" in case of reset
resistor built in
Pull-up resistor
Pull-up resistor
96
TEST0
Input
Test terminal
Pull-up
Normally open
resistor built in
Pull-up resistor
Pull-up resistor
97*
/HSO
Output
Playback speed mode flag output terminal
98*
/UHSO
Output
99
EMPH
Output
Emphasis flag output terminal for sub-code Q data
H: emphasis ON, L: emphasis OFF
Output polarity can be inverted according to commands
H: emphasis ON, L: emphasis OFF
Output polarity can be inverted according to commands
100
LRCK
Output
Channel clock (44.1 kHz) output terminal
L channel: L, R channel: H
Output polarity can be inverted according to commands
L channel: L, R channel: H
Output polarity can be inverted according to commands
Pin No.
Terminal
Name
Input/Output
Function
Remarks
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
/UHSO
H
H
Normal speed playback
H
L
Double speed playback
L
H
4-time speed playback
L
L
8-time speed playback
/HSO
Playback speed
76
DVDD
77
RO
78
DVSS
79
DVR
80
LO
81
DVDD
82
TEST1
83
TEST2
84
TEST3
85
BUS0
86
BUS1
87
BUS2
88
BUS3
89
VDD
90
VSS
91
BUCK
92
/CCE
93
TEST4
94
/TSMOD
95
/RST
96
TEST0
97
/HSO
98
/UHSO
99
EMPH
100
LRCX
50 DMO
49 FVO
48 FMO
47 TEBC
46 RFGC
45 VREF
44 TRO
43 FOO
42 TEZI
41 TEI
40 TSIN
39 SBAD
38 FEI
37 RFRP
36 RFZI
35 RFCT
34 AVDD
33 RFI
32 SLCO
31 AVSS
30 VCOF
29 VCOREF
28 PVREF
27 LPFO
26 LPFN
1
2
3
4
VSS
BCK
AOUT
5
6
7
8
MBOV
IPF
SBOK
CLCK
9 10 11 12
VDD
VSS
DATA
13
SBSY
14
SPCK
15
SPDA
16
COFS
17
MDNIT
18
VDD
19
TESIOO
20
P2VREF
21
SPDO
22
PDOS
23
PDO
24
TMAXS
25
TMAX
SFSY
DOUT
75 74 73 72
XVDD
XO
XI
71 70 69 68
VDD
PXO
PXI
VSS
67 66 65 64
TESIO1
TESIN
/DACT
63
/DMOUT
62
IO3
61
IO2
60
IO1
59
IO0
58
VSS
57
VDD
56
FLGD
55
FLGC
54
FLGB
53
FLGA
52
SEL
51
2VREF
/CKSE
XVSS
LPF
1BIT
DAC
CLOCK
GENERATOR
1 Gk RAM
CLV SERVO
RAM
ROM
DIGITAL
EQUALIZER
EQUALIZER
SERVO
CONTROL
PWM
D/A
A/D
+
-
+
-
+
-
+
-
PWM
VCO
PLL TMAX
MICROCONPUTER
INTERFACE
ADDRESS
CIRCUIT
AUTOMATIC
CONTROL
CIRCUIT
CONTROL
CIRCUIT
CORRECTION
CIRCUIT
EFM DEMODULATION
TO PROTECT
SYNCHRONIZING
SIGNAL
DATA
SLICER
AUDIO
OUTPUT
CIRCUIT
CIRCUIT
DIGITAL OUT
SUB-CODE
DEMODULATION
CIRCUIT
STATUS
Figure 55 BLOCK DIAGRAM OF IC
DX-SX1H
– 56 –
IC801 RH-iX1478GEZZ: System Microcomputer (IX1478GE)
Figure 56 BLOCK DIAGRAM OF IC
MD
2
V
cc
V
cc
V
cc
V
cc
V
cc
V
ss
V
ss
V
ss
V
ss
V
ss
V
ss
V
ss
V
ss
PD
7
/D
15
PD
6
/D
14
PD
5
/D
13
PD
4
/D
12
PD
3
/D
11
PD
2
/D
10
PD
1
/D
9
PD
0
/D
8
PE
7
/D
7
PE
6
/D
6
PE
5
/D
5
PE
4
/D
4
PE
3
/D
3
PE
2
/D
2
PE
1
/D
1
PE
0
/D
0
PA
7
/A
23
/IRQ7
PA
6
/A
22
/IRQ6
MD
1
MD
0
PF
7
/ø
PF
6
/AS
PF
5
/RD
PF
4
/HWR
EXTAL
XTAL
STBY
RES
WDTOVF
NMI
XTAL
STBY
RES
WDTOVF
NMI
PF
3
/LWR
PF
1
/BACK
PF
0
/BREQ
PG
4
/CS0
PG
3
/CS1
PG
2
/CS2
PG
1
/CS3
PG
0
/CAS
P6
7
/CS7/IRQ3
P6
6
/CS6/IRQ2
P6
5
/IRQ1
P6
4
/IRQ0
P6
3
/TEND1
P6
2
/DREQ1
P6
1
/TEND0/CS5
P6
0
/DREQ0/CS4
PF
2
/LCAS/WAIT/BFEQO
PORT 1
PORT 2
PORT 4
P1
0
/PO8/TIOCA0/DACK0
P1
1
/PO9/TIOCB0/DACK1
P1
2
/PO10/TIOCC0/TCLKA
P1
3
/PO11/TIOCD0/TCLKB
P1
4
/PO12/TIOCA1
P1
5
/PO13/TIOCB1/TCLKC
P1
6
/PO14/TIOCA2
P1
7
/PO15/TIOCB2/TCLKD
P2
0
/PO0/TIOCA3
P2
1
/PO1/TIOCB3
P2
2
/PO2/TIOCC3
P2
3
/PO3/TIOCD3
P2
4
/PO4/TIOCA4
P2
5
/PO5/TIOCB4
P2
6
/PO6/TIOCA5
P2
7
/PO7/TIOCB5
P4
7
/AN7/DA1
P4
6
/AN6/DA0
P4
5
/AN5
P4
4
/AN4
P4
3
/AN3
P4
2
/AN2
P4
1
/AN1
P4
0
/AN0
V
ref
AV
cc
AV
ss
PA
5
/A
21
/IRQ5
PA
4
/A
20
/IRQ4
PA
3
/A
19
PA
2
/A
18
PA
1
/A
17
PA
0
/A
16
PB
7
/A
15
PB
6
/A
14
PB
5
/A
13
PB
4
/A
12
PB
3
/A
11
PB
2
/A
10
PB
1
/A
9
PB
0
/A
8
PC
7
/A
7
PC
6
/A
6
PC
5
/A
5
PC
4
/A
4
PC
3
/A
3
PC
2
/A
2
PC
1
/A
1
PC
0
/A
0
P3
5
/SCK1
P3
4
/SCK0
P3
3
/RxD1
P3
2
/RxD0
P3
1
/TxD1
P3
0
/TxD0
P5
0
P5
1
P5
2
P5
3
/ADTRG
PORT E
PORT D
ROM *
RAM
TPU
PPG
A/D CONVERTER
D/A CONVERTER
SCI
WDT
DMAC
DTC
H8S/2000 CPU
CLOCK
OSCILLA
T
O
R
PORT A
PORT B
PORT C
PORT 3
PORT 5
PORT 6
PORT G
PORT F
INTERRUPT
CONTROLLER
INTERNAL DATA BUS
INTERNAL ADDRESS BUS
BUS CONTROLLER
PERIPHERAL DATA BUS
PERIPHERAL ADDRESS BUS
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