Sharp DX-SX1 (serv.man2) Service Manual ▷ View online
DX-SX1H
– 45 –
IC303 VHiPCM1716E-1: CD D/A Converter (PCM1716E)
Figure 45 BLOCK DIAGRAM OF IC
1
LRCK
Input
LRCK clock input (fs)
2
DATA
Input
Data input
3
BCK
Input
Data bit clock input
4*
CLKO
Output
System clock, buffered output
5
XTI
Input
Connection of crystal transmitter or external clock input
6*
XTO
Output
Connection of crystal transmitter
7
DGND
—
Digital GND
8
VDD
—
Digital power supply, +5V
9
VCC2R
—
Analog power supply, +5V
10
AGND2R
—
Analog GND
11
EXTR
Output
Rch, analog output amplifier common
12
NC
—
Not used
13
VOUTR
Output
Rch, analog voltage output
14
AGND1
—
Analog GND
15
VCC1
—
Analog power supply, +5V
16
VOUTL
Output
Lch, analog voltage output
17
NC
—
Not used
18
EXTL
Output
Lch, analog output amplifier common
19
AGND2L
—
Analog GND
20
VCC2L
—
Analog power supply, +5V
21*
ZERO
Output
Zero data flag
22
RST
Input
Reset. While this pin is in "L", DF and delta-sigma modulator are in the reset condition.
23
CS/IWO
Input
Chip select/input format select
24
MODE
Input
Mode control select (H: software, L: hardware)
25
MUTE
Input
Mute control
26
MD/DM0
Input
Mode control data/de-emphasis select 1
27
MC/DM1
Input
Mode control BCK/de-emphasis select 2
28
ML/IIS
Input
Mode control latch/input format select
Pin No. Terminal Name Input/Output
Function
BCK
LRCK
DATA
ML/IIS
MC/DM1
MD/DM0
MD/DM0
CS/IWO
MODE
MUTE
RST
XTI XTO
CLKO
VCC AGND
DGND
VDD
BPZ-Cont.
Crystal OSC
DAC
DAC
OPEN DRAIN
VOUTL
VCC2L
AGND2L
VCC2R AGND2R
EXTL
EXTR
VOUTR
ZERO
SERIAL
INPUT
I/F
MODE
CONTROL I/F
8-TIME
OVERSAMPLING
DIGITAL FILTER
WITH FUNVTION
CONTROLLER
POWER
MULTI-LEVEL
DELTA/SIGMA
MODULATOR
LOW-PASS
FILTER
LOW-PASS
FILTER
DX-SX1H
– 46 –
IC502 RH-iX1517GEZZ: RF Signal Processor (IX1517GE) (1/2)
1
GND
—
GND terminal
—
2
P2TP
Input
TE+ input (CD)
VrA
3
P2TN
Input
TE- input (CD)
VrA
4
LDO2
Output
Drive output
—
5
MDI2
Input
Monitor output
—
6
VrA
Output
Analog VREF
2.1 [V]
7
VrD
Output
Digital VREF
—
1/2 of Vdd (2.1V)
8
VDD
Input
Power terminal
Approx. 4.2V
9
DPAC
—
DPD AC coupling capacity 1
—
10
DPBD
—
DPD AC coupling capacity 2
—
11
DPD1
—
DPD integration capacity 1
—
12
DPD2
—
DPD integration capacity 2
—
13
SCB
Input
Control line (Bit clock)
2.2 [V]
14
SCL
Input
Control line (Latch signal)
2.2 [V]
15
SCD
Input
Control line (Serial data)
2.2 [V]
16
VRCK
Input
Reference clock input
2.3 [V]
Frequency increase results in shift to
higher filter frequency except for servo LPF.
higher filter frequency except for servo LPF.
17
VCKF
—
Time constant adjustment capacity
—
18
VCCP
—
Power terminal
—
19
LVL
Output
Servo addition output
VrD x (1/2)
20
TEO
Output
TE output
VrD
21
FEO
Output
FE output
VrD
22
DFTN
Input
DPD defect
—
DPD output at Low: Mute
23
VCCS
—
Power terminal (Servo)
—
24
RPZ
Output
RF ripple center voltage
VrD
25
RPO
Output
RF ripple output
VrD
26
RPB
Output
RF ripple bottom
—
27
RPP
Output
RF ripple peak
—
28
RFO
Output
Equalizing RF output
2.3 [V]
29,30
NC
—
NC terminal
—
Used by connecting to GND.
31
VCCR
—
Power terminal (RF)
—
32
DPDB
Input
Pit depth adjustment
VrD
DPDB increase brings delay capacity
increase on sides A and B.
increase on sides A and B.
33
TEB
Input
TE balance
VrD
TEB increase brings increase in gain on TP
side and in delay capacity on sides A and C.
side and in delay capacity on sides A and C.
34
FEB
Input
FE balance
VrD
FEB increase brings increase in gain on
sides A and C (FP).
sides A and C (FP).
35
PSC
Input
VRCK frequency division ON/OFF
—
Frequency division OFF at High
36
VCC2
—
Power terminal
—
37
NC
—
NC terminal
VrD
Connected to GND via C.
38
EQD
Input
Group delay correction
VrD
Group delay by raising EQD: rise rightward
39
GND2
—
GND terminal
—
40
RFDC
—
DC feedback capacity
—
41*
RFA
Output
RF total adding output
2.2 [V]
42
EQB
Input
Boost adjustment
VrD
Boost quantity up by raising EQB.
43
EQF
Input
Frequency adjustment
VrD
Shift to higher frequency by raising EQF.
44
MDI1
Input
Monitor input
—
45
LDO1
Output
Drive output
—
46
P1TN
Input
TE- input (DVD)
VrA
47
P1TP
Input
TE+ input (DVD)
VrA
48
NC
—
NC terminal
—
Used by connecting to GND.
49
P1FN
Input
FE- input (DVD)
VrA
Pin No. Terminal Name Input/Output
Function
Terminal DC
Voltage (TYP.)
Remarks
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
DX-SX1H
– 47 –
Figure 47 BLOCK DIAGRAM OF IC
IC502 RH-iX1517GEZZ: RF Signal Processor (IX1517GE) (2/2)
50
P1FP
Input
FE+ input
VrA
51
LDP1
Input
APC polarity 1
—
Positive polarity when connecting to Vcc
52
P1DI
Input
D input (DVD)
VrA
53
P1CI
Input
C input (DVD)
VrA
54
P1BI
Input
B input (DVD)
VrA
55
P1AI
Input
A input (DVD)
VrA
56
GNDR
—
GND terminal (RF)
—
57
LDP2
Input
APC polarity 2
—
Positive polarity when connecting to Vcc
58
P2AI
Input
A input (CD)
VrA
59
P2BI
Input
B input (CD)
VrA
60
P2CI
Input
C input (CD)
VrA
61
P2DI
Input
D input (CD)
VrA
62
GNDS
—
GND terminal (Servo)
—
63
P2FP
Input
FE+ input
VrA
64
P2FN
Input
FE- input
VrA
Pin No. Terminal Name Input/Output
Function
Terminal DC
Voltage (TYP.)
Remarks
P1FN
P1FP
LDP1
P1DI
P1CI
P1BI
P1AI
GNDR
LDP2
P2AI
P2BI
P2CI
P2DI
GNDS
P2FP
P2FN
DPDB
VccR
NC
NC
RFO
RPP
RPB
RPO
RPZ
VccS
DFTN
FEO
TEO
LVL
LccP
VCKF
NC
P1TP
P1TN
LDO1
MDI1
EQF
EQB
RFA
RFDC
GND2
EQD
NC
Vcc2
PSC
FEB
TEB
GND
P2TP
P2TN
LDO2
MDI2
VrA
VrD
Vdd
DPAC
DPBD
DPD1
DPD2
SCB
SCL
SCD
SRCK
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
APC1
sel-RF
R-gain
ADJUSTMENT
EQ
F-gain
ADJUSTMENT
F-gain
ADJUSTMENT
RF RIPPLE
GENERATION
FE
GENERATION
DPDTE
GENERATION
FE-gain
ADJUSTMENT
TE-gain
ADJUSTMENT
Level
DETECTION
T-gain
ADJUSTMENT
3BTE
GENERATION
APC2
BUS
sel-PD
sel-PD
sel-PD
mode-TE
sel-FE
sel-IC
sel-TE
sel-DPD
sel-LVL
Time
constant
adjustment
DX-SX1H
– 48 –
IC503 VHiTB6504F+-1: Stepping Motor Driver (TB6504F)
1
CK1
Clock signal input
2, 3
M1, M2
Excitation mode set terminal
4
REF IN
Output reference value (VNF) set terminal H: VNF=0.5V, L: VNF=0.25V
5*
MO
Monitor output L: Initial condition
6*
NC
Not used
7
VCC
Logic side power terminal
8
VMB
Output side power terminal
9
øB
B output
10
PG-B
Power ground
11
NFB
B channel current detection terminal
12
øB
B output
13
øA
A output
14*
NFA
A channel current detection terminal
15
PG-A
Power ground
16
øA
A output
17
VMA
Output side power terminal
18*
NC
Not used
19
S-GND
Signal ground
20
RESET
Reset signal input
21
ENABLE
Enable signal input
22
OSC
Internal oscillation frequency set terminal. Capacitor is externally mounted.
23
CW/CCW
Clockwise/counterclockwise input
24
CK2
Clock signal input
Pin No.
Terminal Name
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Function
Figure 48 BLOCK DIAGRAM OF IC
7
VCC
5
MO
17
16
13
YMA
ØA
ØA IA
14
NFA
8
VMB
12
9
ØB
11
10
NFB
ØB IB
PG-B
(POWER
GROUND B)
(POWER
GROUND B)
15
PG-A
(POWER
GROUND A)
(POWER
GROUND A)
19
4
SG
(SIGNAL GROUND)
(SIGNAL GROUND)
REF IN
22
OSC
21
ENABLE
20
RESET
24
CK2
23
CW/CCW
1
CK1
3
M2
2
M1
O S C
+
+
+
+
BRIDGE
DRIVER
ENABLE
RESET
BRIDGE
DRIVER
ENABLE
RESET
DECODER
DECODER
DECODER
DECODER
SET CURRENT
VALUE SELECTOR
CIRCUIT
SET CURRENT
VALUE SELECTOR
CIRCUIT
MAXIMUM
CURRENT
CURRENT
SELECTOR
CIRCUIT
CK1
M1
M2
REF IN
MO
NC
VCC
VMB
ØB
PG-B
NFB
ØB
CK2
CW/CCW
OSC
ENABLE
RESET
S-GND
NC
VMA
ØA
PG-A
NFA
ØA
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
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