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– 49 –

In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.

1

PG

Power GND terminal

15

SG

Signal GND terminal

2

H1+

Hall element 1 positive input terminal

16

VCC

Power terminal

3

H1-

Hall element 1 negative input terminal

17

ECR

Torque instruction reference input terminal

4*

NC

Not used

18

EC

Torque instruction input terminal

5

H2+

Hall element 2 positive input terminal

19*

NC

Not used

6

H2-

Hall element 2 negative input terminal

20

PCI

Current feedback phase compensating terminal

7

VH

Hall bias terminal

21

VM

Motor power terminal

8

H3+

Hall element 3 positive input terminal

22

CS1

Current detection terminal 1

9

H3-

Hall element 3 negative input terminal

23*

NC

Not used

10

SS

Start/Stop switching terminal

24*

NC

Not used

11*

TFLG

Thermal protection monitor terminal

25*

NC

Not used

12

FG

FG signal output terminal

26

A3

Drive output 3

13

BRK

Break mode set terminal

27

A2

Drive output 2

14*

NC

Not used

28

A1

Drive output 1

2

H1+

3

H1-

5

H2+

8

H3+

6

H2-

9

H3-

7

VH

18

EC

17

10

ECR

S/S

16

Vcc

20

PCI

13

BRK

11

TSDF

12 FG

1 PG

26 A3

27 A2

28 A1

22 CS1

21 VM

15

SG

ER

EA

VTL

EP=ER x EA

FG

COMPARATOR

+   -

MATRIX HALL AMPLIFIER

DETE-

CTION

DIRECTION

DETECTION

DIRECTION SWITCHING

UPPER-SIDE

DISTRIBUTION

AMPLIFICATION

AMPLIFICATION

LOWER-SIDE

DISTRIBUTION

HALL BIAS

LOGIC

ABSOLUTE

VALUE

START/

STOP

THERMAL

PROTECTION

CIRCUIT

BREAK

CIRCUIT

– 50 –

Note 1: Positive output/negative output means polarity toward input. (Ex. 18 pin output 'H' in case of 19 pin input 'H')
Note 2: Tray positive output/tray negative output means polarity toward mode. (Ex. 11 pin output 'H' in case of the forward mode)
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.

1*

OPOUT

Operational amplifier output terminal

15

CH2-OUT-

CH2 negative output terminal

2

CH4-IN

CH4 input terminal

16

CH2-OUT+

CH2 positive output terminal

3*

CH4-IN'

CH4 gain adjustment input terminal

17

CH1-OUT-

CH1 negative output terminal

4

CTL1

Control 1 input terminal

18

CH1-OUT+

CH1 positive output terminal

5

CTL2

Control 2 input terminal

19

CH1-IN

CH1 input terminal

6

FWD

Tray forward input terminal

20

CH1-IN'

CH1 gain adjustment input terminal

7

REV

Tray reverse input terminal

21

VCC

VCC

8

TRAY-IN

Tray input terminal

22

CH2-IN

CH2 input terminal

9

GND

Substrate GND

23*

CH2-IN'

CH2 gain adjustment input terminal

10

CH5-OUT-

Tray negative output terminal

24*

CH3-IN

CH3 input terminal

11

COM-OUT

Tray positive terminal/CH4 negative output terminal

25*

CH3-IN'

CH3 gain adjustment input terminal

12*

CH4-OUT+

CH4 positive output terminal

26

VREF-IN

Bias amplifier input terminal

13*

CH3-OUT+

CH3 positive output terminal

27*

OPIN+

Operational amplifier non-inversion input terminal

14*

CH3-OUT-

CH3 negative output terminal

28*

OPIN-

Operational amplifier inversion input terminal

28

27

26

25

24

23

22

21

20

19

18

17

16

15

CH2-OUT

CH1-OUT

CH1-IN

CH2-IN

CH3-IN

10K

10K

13.3K

13.3K

13.3K

10K

+

-

VCC

D

D

D

D

D

D

D

D

D

V/I

T.S.D

26.6K

10K

CTL1

CTL2

PWD

REV

LOGIC

1

2

3

4

5

6

7

8

9

10

11

12

13

14

CH4-IN

CH5-IN

CH5-OUT CH4-OUT CH3-OUT

+

-

+

-

+

-

+

-

LEVEL SHIFT

LEVEL SHIFT

LEVEL SHIFT

LEVEL SHIFT

For CTL1 and CTL2

L

L

OFF

ON

L

H

H

L

ON

OFF

H

H

OFF

ON

OFF

ON

Note: Output: high impedance in case of OFF.

For F and R (CH5 control is effective only in case of ON)

L

L

High impedance

L

H

Reverse

H

L

Forward

H

H

Break

– 51 –

1

DPCKI

Input

Signal processing reference clock input

0.5 - 3.3Vpp, feedback resistor built in.

2

DVDD3

—

Digital power supply (3.3V)

For logic cell

3

SVCKI

Input

Servo reference clock input (Oscillation circuit input terminal)

3.3V-I/F feedback resistor built in

4*

SVCKO

Output

Servo reference clock input (Oscillation circuit input terminal)

5

DVSS

—

Digital power supply (0V)

For logic cell

6

DVDD3

—

Digital power supply (3.3V)

For logic cell

7*

NC

—

The use forbidden

Open

8

HDWT

Input

MPU write signal

Level TTL

9

HDRD

Input

MPU read signal

Level TTL

10

HCEN

Input

MPU chip select

Level TTL

11-18

HD0-HD7

Input/Output MPU data bus

Level TTL

19

DVSS

—

Digital power supply (0V)

For I/O cell

20

DVDD5

—

Digital power supply (5V)

For I/O cell

21

HINT

Output

MPU interrupt signal (Occurrence of interruption = "L")

OPEN DRAIN

22,23

HA0, HA1

Input

MPU address bus

Level TTL

24

PLCK

Output

Read channel clock output terminal

25*-31* ED0-ED6

—

For default adjustment; use by user is forbidden. (NC)

Open

32

ED7

Output

SACD 2 binary data

33

TEST

Input

For default adjustment

Set to "L".

34

PDON

Output

PLL phase error signal output (Polarity: -)

35

PDOP

Output

PLL phase error signal output (Polarity: +)

36

RLLD

Output

PLL detection result output

37

LPFN

Input

Inversion input of amplifier for PLL loop filter

38

LPFO

Output

Output of amplifier for PLL loop filter

39

VCOF

Output

VCO filter terminal

40

SCLO

Output

Reference voltage output terminal of built-in comparator

41

AVSS

—

Analog power supply (0V)

42

AVR

Output

Non-PLL analog reference potential (1.65V)

43

VRC

—

Resistance dividing point potential
(For generating analog reference potential: 1.65)

44

PVR

Output

PLL analog reference potential (1.65V)

45

AVDD

—

Analog power supply (3.3V)

46

RVR2

—

Secondary reference voltage (For connecting capacitor)

47

RVDD

—

Dedicated power terminal (3.3V)

48

RFIN

Input

RF signal input

49

RVSS

—

Dedicated power terminal (0V)

50

RVR1

—

The first reference voltage (For connecting capacitor)

51

DVR

Input

DMO reference potential (1.65V recommended)

52

DMO

Output

DVD disc equalizer output (Ternary PWM + Hiz)

53

RASN

Output

External RAM column address select (Negative logic)

54

CASN

Output

External RAM row address select (Negative logic)

55

MOEN

Output

External RAM output enable signal

56

MWEN

Output

External RAM read/ write select

57

DVSS

—

Digital power supply (0V)

For logic cell

58

DVDD3

—

Digital power supply (3.3V)

For logic cell

59-68

MA9-MA0

Output

External RAM address bus

69

DVSS

—

Digital power supply (0V)

For I/O cell

70

DVDD5

—

Digital power supply (5V)

For I/O cell

71-78

MD7-MD0

Input/Output External RAM data bus

Level TTL

79-82

SD7-SD4

Output

MPEG data output

83

DVSS

—

Digital power supply (0V)

For logic cell

In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.

– 52 –

84

DVDD3

—

Digital power supply (3.3V)

For logic cell

85-88

SD3-SD0

Output

MPEG data output

89

SERR

Output

MEPG data reliability flag (Data error = "L")

90

SBGN

Output

MEPG output sector synchronous signal (Sector head = "L")

91

SENB

Output

MEPG data effective flag (Effective = "L")

92

SDCK

Output

MEPG data transfer clock

93

DVSS

—

Digital power supply (0V)

For logic cell

94

SREQ

Input

MEPG data request flag (In case of request = "L")

Level TTL

95

RSTN

Input

Hard reset input (In case of reset = "L")

96

DVDD3

—

Digital power supply (3.3V)

For logic cell

97

STDA

Output

Status data output

98

STCK

Output

Status clock output

99

UPWM

Output

Universal PWM output

100

DVSS

—

Digital power supply (0V)

For logic cell

10-13, 16-20, 9

A0-A8, A9R

Address input

8

RAS

Row address strobe

23

CAS

Column address strobe

2-5, 24-27

DQ1-DQ8

Data input/Data output

22

OE

Output enable

7

WE

Write enable

1

VCC

Power supply (5V)

15, 28

VSS

Ground (0V)

6*, 21*

NC

Not used

In this unit, the terminal with asterisk mark (*) is (open)
terminal which is not connected to the outside.

Timing

Generator

Timing

Generator

Column

Address

Buffers

Internal

Address

Counter

Row

Address

Buffers

Refresh

Control Clock

Column

Decoders

Sense

Ampliliers

Write

Clock

Generator

I/O

Selector

Output

Buffers

Input

Buffers

Row

De-

coders

Word

Drivers

Memory

Cells

On Chip

Vcc Generator

RAS

CAS

A0 ~ A8

A9R

Vcc

Vcc

Vss

Vss

WE

OE

DO1 ~ DO8

9

9

1

10

9

8

8

8

8

8

8

8