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– 57 –

1

VDD

—

Power supply +3.3V

2-4

HADR0-HADR2

Input

CPU address bus

5

HCS

Input

CPU chip select

6

HWR

Input

CPU write signal

7

HRD

Input

CPU read signal

8-15

HDAT0-HDAT7

Input/Output

CPU data bus

16

VSS

—

Digital GND

17

VDD

—

Power supply +3.3V

18

EXPPAL0, SLDCK 1

Output

Driving clock output for stepping motor driver

19

EXPPAL1, SLDCK 2

Output

Mode control output for stepping motor driver

20

EXPPAL2, CW/CCW

Output

Rotating direction control output for stepping motor driver

21

EXPPAL3, DACCK

Output

Clock signal for electronic capacity IC

22

EXPPAU0, DACDT

Output

Data signal for electronic capacity IC

23*

EXPPAU1

Input/Output

General input/output terminal Gr.A

24

VSS

—

Digital GND

25

VDD

—

Power supply +3.3V

26

EXPPAU2

Input

General input/output terminal Gr.A

27

EXPPAU3

Output

General input/output terminal Gr.A

28

EXPBL0, EXTCK

Output

Control clock output to 1-bit amplifier

29

EXPBL1, EXTDO

Output

Control data output to 1-bit amplifier

30

EXPBL2, EXTST

Output

Control strobe output to 1-bit amplifier

31

EXPBL3, VOLCS

Output

Chip select signal for electronic capacity IC

32

VSS

—

Digital GND

33

VDD

—

Power supply +3.3V

34

EXPBU0, EXTDI

Input

Control data input from 1-bit amplifier

35

EXPBU1, MECSW1

Input

Tray position detection input

36

EXPBU2, MECSW2

Input

Mechanism stop mode detection input

37

EXPBU3, SMODE

Input

Operating mode set input. Opened (S-MODE)

38

EXPC0, DVD_L

Output

SACD disc inserted/CD stopped: L

39

EXPC1, SMUTE

Output

Soft mute signal for SACD decoder

40

EXPC2, AMUTE

Output

Audio mute. In case of playback/manual search

41

VSS

—

Digital GND

42

EXPC3

Input/Output

General input/output terminal Gr.C

43

EXPC4, DSDCTL

Output

Output control signal for DSD 1-bit signal

44

EXPC5, SEEK

Output

General input/output terminal Gr.C

45

EXPD0, GAIN0

Output

Gain control signal for RF pre-amplifier

46

EXPD1, GAIN1

Output

Gain control signal for RF pre-amplifier

47

EXPD2, GAIN2

Output

Gain control signal for RF pre-amplifier

48

VSS

—

Digital GND

49

VDD

—

Power supply +3.3V

50

EXPD3, MMUTE

Output

Main relay control signal. After reading disc TOC: "H"

51

EXPD4

Input/Output

General input/output terminal Gr.D

52

EXPD5, EMPH

Output

De-emphasis signal output

53

BUFDO, RST_01

Output

Buffer output D/Reset signal output for peripheral IC

54

BUFDI

Input

Buffer input D

55

SBUFBO

Output

Schmitt buffer output B

56

SBUFBI

Input

Schmitt buffer input B

57

SBUFAO

Output

Schmitt buffer output A

58

SBUFAI

Input

Schmitt buffer input A

59

MRST

Input

Reset terminal

In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.

– 58 –

60

MODE

Input

Mode switching terminal. Fix at "L".

61

BUFCO

Input/Output

Buffer output C

62

TEST

Input

Test terminal. Fixed at "L".

63

BUFCI

Input

Buffer input C. Not used.

64

VSS

—

Digital GND

Pins 1 to 15: Simultaneous changes possible. Operating frequency: approx. 10MHz
Pins 18 to 47: Simultaneous changes possible. (Static signal) Operating frequency: approx. 1kHz
Pins 50 to 57: Simultaneous changes almost impossible. Operating frequency: approx. 1kHz

Data Buffer

Latch D

Data Buffer

Latch C

Data Buffer

Latch B

Data Buffer

Latch A

Data Buffer

R/W CTL

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

32

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

VDD

EXPD(3)

EXPD(4)

EXPD(5)

BUFDO

BUFDI

SBUFBO

SBUFBI

SBUFAO

SBUFAI

MRST

MODE

BUFCO

TEST

BUFCI

VSS

VSS

EXPBL(3)

EXPBL(2)

EXPBL(1)

EXPBL(0)

EXPAU(3)

EAPAU(2)

VDD

VSS

EXPAU(1)

EXPAU(0)

EXPAL(3)

EAPAL(2)

EXPAL(1)

EAPAL(0)

VDD

VSS

Q2(3)

Q2(2)

Q2(1)

Q2(0)

Q1(7)

Q1(6)

VDD

VSS

Q1(5)

A1(4)

Q1(3)

Q1(2)

Q1(1)

Q1(0)

VDD

VDD

SOUT(3)

SOUT(4)

SOUT(5)

MRST

MODE

SEL

TEST

CK

VSS

VSS

EXPD(2)

EXPD(1)

EXPD(0)

EXPC(5)

EXPC(4)

EXPC(3)

VSS

EXPC(2)

EXPC(1)

EXPC(0)

EXPBU(3)

EXPBU(2)

EXPBU(1)

EXPBU(0)

VDD

VDD

HADR0

HADR1

HADR2

HCS

HWR

HRD

HDAT0

HDAT1

HDAT2

HDAT3

HDAT4

HDAT5

HDAT6

HDAT7

VSS

VDD

D(0)

D(1)

D(2)

D(3)

D(4)

D(5)

D(6)

D(7)

S1(0)

S1(1)

S1(2)

S1(3)

S1(4)

S1(5)

VSS

VSS

SOUT(2)

SOUT(1)

SOUT(0)

S2(5)

S2(4)

S2(3)

VSS

S2(2)

S2(1)

S2(0)

Q2(7)

Q2(6)

Q2(5)

Q2(4)

VDD

INPUT/

OUTPUT

PINS

INPUT/OUTPUT

PINS

INPUT/OUTPUT PINS

OPEN DRAIN WHEN

OUTPUTTING

INPUT/OUTPUT

PINS

INPUT/OUTPUT

PINS

INPUT/

OUTPUT

PINS

DEDICATED

PINS

– 59 –

1*

NC

Not used

2

A16

Address input

3

A14

Address input

4

A12

Address input

5-12

A7-A0

Address input

13-15

I/O1-I/O3

Data input/output

16

GND

Ground

17-21

I/O4-I/O8

Data input/output

22

CE1

Chip enable input

23

A10

Address input

24

OE

Output enable input

25

A11

Address input

26, 27

A9, A8

Address input

28

A13

Address input

29

R/W

Read/Write input

30

CE2

Chip enable input

31

A15

Address input

32

VDD

Power terminal (+5V)

In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.

A4

CE

A5

A6

A7

A8

A12

A13

A14

A15

A16

I/O1

I/O8

OE

R/W

CE1

CE2

MEMORY CELL 

ARRAY

1024 x 28 x 8

(1048576)

VDD

GND

~

CE

A0

A1

A2

A3

A9

A10

A11

CE

ROW ADDRESS

BUFFER

ROW ADDRESS

REGISTER

ROW ADDRESS

DECODER

DATA CONTROL

CLOCK

GENERATOR

SENSE AMPLIFIER

COLUMN ADDRESS

DECODER

COLUMN ADDRESS

REGISTER

COLUMN ADDRESS

BUFFER

(TOP VIEW)

N.C.

A16

A14

A12

A7

A6

A5

A4

A3

A2

A1

A0

I/O1

I/O2

I/O3

GND

VDD

A15

CE2

R/W

A13

A8

A9

A11

OE

A10

CE1

I/O8

I/O7

I/O6

I/O5

I/O4

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

– 60 –

1-3

A15-A13

Input

Block select addresses: Select 1/32 erase block. These addresses are latched during data entry,
erase and lock block.

4-8

A12-A8

Input

Word select addresses: Select one word in 1.6k byte block.
These addresses are latched during data entry.

9*, 10*

NC

—

Not used

11

WR

Input

Write enable: Controls access to command user interface, to data cue register and to address
cue latch. At Low, WR is active to input address and data at leading edge.

12

/RP

Input

Reset/power-down: By setting /RP at Low, control circuit is initialized when supplying power.
When supplying/breaking power, /RP pin is maintained at Low to protect data.
If /RP is at Low, device is in condition of deep power down.
To return from the deep power down, 480ns is required.
When pin /RP is at Low, all chip operation is interrupted and reset.
After return, device reads array.

13

VPP

—

Device power supply: 5.0 V

14

/WP

—

Write/Erase power supply: 5.0

±

0.5V is applied during the writing/erasing operation.

15

RY/BY

Output

Ready/Busy: Outputs the condition of the internal write state machine. "Low" shows the write
state machine is in operation. When the machine is waiting for the next instruction to operate,
interrupting erasing, or in deep power-down condition, RY/BY pin is in the float condition.

16,17

A18, A17

Input

Block select addresses: Select 1/32 erase block. These addresses are latched during data entry,
erase and lock block.

18-25

A7-A0

Input

Word select addresses: Select one word in 1.6k byte block.
These addresses are latched during data entry.

26

/CE

Input

Chip enable: Makes control logic, input buffer, decoder, and sense amplifier of the device active.
Only when /CE is Low, chip becomes active.

27

GND

—

Ground

28

/OE

Input

Output enable: By setting /OE at Low, data are output from pin DQ.
If /OE is set at High, pin DP becomes in the float condition.

29

DQ0

Input/Output

Lower byte data input/output: Data and command input during cycle of writing command user
interface. Memory array, identifier, and status data output when reading various data.
Float condition in case of chip non-select or output disable.

30

DQ8

Input/Output

Upper byte data input/output: The function is the same as shown in case of the lower byte data
input/output above. Operating only in x16 mode. Floating in x 8 mode. DQ15/A-1: address

31

DQ1

Input/Output

Lower byte data input/output: Data and command input during cycle of writing command user
interface. Memory array, identifier, and status data output when reading various data.
Float condition in case of chip non-select or output disable.

32

DQ9

Input/Output

Upper byte data input/output: The function is the same as shown in case of the lower byte data
input/output above. Operating only in x16 mode. Floating in x 8 mode. DQ15/A-1: address

33

DQ2

Input/Output

Lower byte data input/output: Data and command input during cycle of writing command user
interface. Memory array, identifier, and status data output when reading various data.
Float condition in case of chip non-select or output disable.

34

DQ10

Input/Output

Upper byte data input/output: The function is the same as shown in case of the lower byte data
input/output above. Operating only in x16 mode. Floating in x 8 mode. DQ15/A-1: address

35

DQ3

Input/Output

Lower byte data input/output: Data and command input during cycle of writing command user
interface. Memory array, identifier, and status data output when reading various data.
Float condition in case of chip non-select or output disable.

36

DQ11

Input/Output

Upper byte data input/output: The function is the same as shown in case of the lower byte data
input/output above. Operating only in x16 mode. Floating in x 8 mode. DQ15/A-1: address

37

VCC

—

Device power supply: 5.0

±

0.5V

38

DQ4

Input/Output

Lower byte data input/output: Data and command input during cycle of writing command user
interface. Memory array, identifier, and status data output when reading various data.
Float condition in case of chip non-select or output disable.

39

DQ12

Input/Output

Upper byte data input/output: The function is the same as shown in case of the lower byte data
input/output above. Operating only in x16 mode. Floating in x 8 mode. DQ15/A-1: address

40

DQ5

Input/Output

Lower byte data input/output: Data and command input during cycle of writing command user
interface. Memory array, identifier, and status data output when reading various data.
Float condition in case of chip non-select or output disable.

41

DQ13

Input/Output

Upper byte data input/output: The function is the same as shown in case of the lower byte data
input/output above. Operating only in x16 mode. Floating in x 8 mode. DQ15/A-1: address

In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.