Panasonic KX-PX1EX Service Manual ▷ View online
21
KX-PX1EX
349
D8
SDWP
SD card write pro-
tect input
tect input
Input the SD card write enable
N.C. 33k
Pull_UP
Pull_UP
Not used
in
316
AB23 TCK
Test ClocK
Test clock terminal
Low GND
Not used
in
234
AD23 TDC
Test Input
Fixed to the "L" level on the board Low GND
Not used
in
237
AB24 TDI
Test Data Input
Test data input terminal
N.C.
Not used
in
236
AC24 TDO
Test Data Output
Test data output terminal
N.C.
Not used
out
145
AE23 TEST-
MODE
TEST MODE Input
Fixed to the "L" level on the board Low GND
Not used
in
150
AB25 TMS
Test Mode Select
Test mode selection terminal
N.C.
Not used
in
119
Y2 TOPFIELD
/
TOPFIELD
#
TOPFIELD
#
Top field
Indicate that the top field is being
displayed.The polarity is pro-
grammable
displayed.The polarity is pro-
grammable
CL128
Not used
out
55
AB26 TRST#
Test ReSeT
Input the same signal with
PRST# when not using the JTAG
function
PRST# when not using the JTAG
function
FR_RST#
CPU_*PRST
CPU_*PRST
Reset input
in
191
B4
UDM
USB(F) D -signal
Differential signal of the USB
function (-)
function (-)
USB(F) D-
UDM_F
UDM_F
USB-F(D-)
USB-F (device) data (-)
USB-F (device) data (-)
I/O
278
E4
UDM1
USB(Host) D -signal Differential signal of the USB host
(-)
USB(H) D-
UDM_H
UDM_H
USB-H(D-)
USB-H (Host) data (-)
USB-H (Host) data (-)
I/O
276
C4
UDP
USB(F) D +signal
Differential signal of the USB
function (+)
function (+)
USB(F) D+
UDP_F
UDP_F
USB-F(D+)
USB-F (device) data (+)
USB-F (device) data (+)
I/O
353
E5
UDP1
USB(Host) D+signal Differential signal of the USB host
(+)
USB(H) D+
UDP_H
UDP_H
USB-H(D+)
USB-H (Host) data (+)
USB-H (Host) data (+)
I/O
190
B5
USCKI
USB clock input
Input the clock for the USB inter-
face
face
USB_CLK
48MHz
48MHz
USB_CLK 48MHz
USB clock 48MHz
USB clock 48MHz
in
110
L2 VCB[0]/
AVPP[24]
B component input/
C component input/
Cb component input/
GPIO
C component input/
Cb component input/
GPIO
Input of the video data for captur-
ing. Common terminal with GPIO.
Input of GPIO after a reset.
ing. Common terminal with GPIO.
Input of GPIO after a reset.
N.C.
(The pin
should be set
to the output
mode)
(The pin
should be set
to the output
mode)
Not used
out
11
L1 VCB[1]/
AVPP[25]
B component input/
C component input/
Cb component input/
GPIO
C component input/
Cb component input/
GPIO
Input of the video data for captur-
ing. Common terminal with GPIO.
Input of GPIO after a reset.
ing. Common terminal with GPIO.
Input of GPIO after a reset.
N.C.
(The pin
should be set
to the output
mode)
(The pin
should be set
to the output
mode)
Not used
out
360
M5 VCB[2]/
AVPP[26]
B component input/
C component input/
Cb component input/
GPIO
C component input/
Cb component input/
GPIO
Input of the video data for captur-
ing. Common terminal with GPIO.
Input of GPIO after a reset.
ing. Common terminal with GPIO.
Input of GPIO after a reset.
N.C.
(The pin
should be set
to the output
mode)
(The pin
should be set
to the output
mode)
Not used
out
285
M4 VCB[3]/
AVPP[27]
B component input/
C component input/
Cb component input/
GPIO
C component input/
Cb component input/
GPIO
Input of the video data for captur-
ing. Common terminal with GPIO.
Input of GPIO after a reset.
ing. Common terminal with GPIO.
Input of GPIO after a reset.
N.C.
(The pin
should be set
to the output
mode)
(The pin
should be set
to the output
mode)
Not used
out
202
M3 VCB[4]/
AVPP[28]
B component input/
C component input/
Cb component input/
GPIO
C component input/
Cb component input/
GPIO
Input of the video data for captur-
ing. Common terminal with GPIO.
Input of GPIO after a reset.
ing. Common terminal with GPIO.
Input of GPIO after a reset.
N.C.
(The pin
should be set
to the output
mode)
(The pin
should be set
to the output
mode)
Not used
out
111
M2 VCB[5]/
AVPP[29]
B component input/
C component input/
Cb component input/
GPIO
C component input/
Cb component input/
GPIO
Input of the video data for captur-
ing. Common terminal with GPIO.
Input of GPIO after a reset.
ing. Common terminal with GPIO.
Input of GPIO after a reset.
N.C.
(The pin
should be set
to the output
mode)
(The pin
should be set
to the output
mode)
Not used
out
12
M1 VCB[6]/
AVPP[30]
B component input/
C component input/
Cb component input/
GPIO
C component input/
Cb component input/
GPIO
Input of the video data for captur-
ing. Common terminal with GPIO.
Input of GPIO after a reset.
ing. Common terminal with GPIO.
Input of GPIO after a reset.
N.C.
(The pin
should be set
to the output
mode)
(The pin
should be set
to the output
mode)
Not used
out
112
N2 VCB[7]/
AVPP[31]
B component input/
C component input/
Cb component input/
GPIO
C component input/
Cb component input/
GPIO
Input of the video data for captur-
ing. Common terminal with GPIO.
Input of GPIO after a reset.
ing. Common terminal with GPIO.
Input of GPIO after a reset.
N.C.
(The pin
should be set
to the output
mode)
(The pin
should be set
to the output
mode)
Not used
out
357
J5 VCD-
CLKIN
Capture pixel clock
input
input
Sampling clock for capturing
Low 33k
Pull_Down
Pull_Down
Not used
in
pin
No.
pin
assign
ment
Name of
the CPU
the CPU
terminal
VDE
VDD
Signal name
of the CPU
(IC3) on the
main board
Purpose of the signal
I/O
22
KX-PX1EX
6
F1
VCG[0]
G component input/
Y component input/
YC multiplex input
Y component input/
YC multiplex input
Input of the video data for captur-
ing
ing
Low
Not used
in
355
G5
VCG[1]
G component input/
Y component input/
YC multiplex input
Y component input/
YC multiplex input
Input of the video data for captur-
ing
ing
Low
Not used
in
280
G4
VCG[2]
G component input/
Y component input/
YC multiplex input
Y component input/
YC multiplex input
Input of the video data for captur-
ing
ing
Low
Not used
in
197
G3
VCG[3]
G component input/
Y component input/
YC multiplex input
Y component input/
YC multiplex input
Input of the video data for captur-
ing
ing
Low
Not used
in
106
G2
VCG[4]
G component input/
Y component input/
YC multiplex input
Y component input/
YC multiplex input
Input of the video data for captur-
ing
ing
Low
Not used
in
7
G1
VCG[5]
G component input/
Y component input/
YC multiplex input
Y component input/
YC multiplex input
Input of the video data for captur-
ing
ing
Low
Not used
in
356
H5
VCG[6]
G component input/
Y component input/
YC multiplex input
Y component input/
YC multiplex input
Input of the video data for captur-
ing
ing
Low
Not used
in
281
H4
VCG[7]
G component input/
Y component input/
YC multiplex input
Y component input/
YC multiplex input
Input of the video data for captur-
ing
ing
Low
Not used
in
198
H3 VCH-
SYNC/
VCH-
SYNC#
VCH-
SYNC#
Horizontal synchro-
nous signal input
nous signal input
Synchronous signal input for cap-
turing. The polarity is programma-
ble.
turing. The polarity is programma-
ble.
Low
Not used
in
108
J2 VCR[0]/
AVPP[8]
R component input/
Cr component input/
GPIO
Cr component input/
GPIO
Input of the video data for captur-
ing. Common terminal with GPIO.
Input of GPIO after a reset.
ing. Common terminal with GPIO.
Input of GPIO after a reset.
N.C.
(The pin
should be set
to the output
mode)
(The pin
should be set
to the output
mode)
Not used
out
9
J1 VCR[1]/
AVPP[9]
R component input/
Cr component input/
GPIO
Cr component input/
GPIO
Input of the video data for captur-
ing. Common terminal with GPIO.
Input of GPIO after a reset.
ing. Common terminal with GPIO.
Input of GPIO after a reset.
N.C.
(The pin
should be set
to the output
mode)
(The pin
should be set
to the output
mode)
Not used
out
358
K5 VCR[2]/
AVPP[10]
R component input/
Cr component input/
GPIO
Cr component input/
GPIO
Input of the video data for captur-
ing. Common terminal with GPIO.
Input of GPIO after a reset.
ing. Common terminal with GPIO.
Input of GPIO after a reset.
N.C.
(The pin
should be set
to the output
mode)
(The pin
should be set
to the output
mode)
Not used
out
283
K4 VCR[3]/
AVPP[11]
R component input/
Cr component input/
GPIO
Cr component input/
GPIO
Input of the video data for captur-
ing. Common terminal with GPIO.
Input of GPIO after a reset.
ing. Common terminal with GPIO.
Input of GPIO after a reset.
N.C.
(The pin
should be set
to the output
mode)
(The pin
should be set
to the output
mode)
Not used
out
200
K3 VCR[4]/
AVPP[12]
R component input/
Cr component input/
GPIO
Cr component input/
GPIO
Input of the video data for captur-
ing. Common terminal with GPIO.
Input of GPIO after a reset.
ing. Common terminal with GPIO.
Input of GPIO after a reset.
N.C.(The pin
should be set
to the output
mode)CL170
should be set
to the output
mode)CL170
Not used
out
109
K2 VCR[5]/
AVPP[13]
R component input/
Cr component input/
GPIO
Cr component input/
GPIO
Input of the video data for captur-
ing. Common terminal with GPIO.
Input of GPIO after a reset.
ing. Common terminal with GPIO.
Input of GPIO after a reset.
N.C.(The pin
should be set
to the output
mode)CL169
should be set
to the output
mode)CL169
Not used
out
10
K1 VCR[6]/
AVPP[14]
R component input/
Cr component input/
GPIO
Cr component input/
GPIO
Input of the video data for captur-
ing. Common terminal with GPIO.
Input of GPIO after a reset.
ing. Common terminal with GPIO.
Input of GPIO after a reset.
N.C. (The pin
should be set
to the output
mode)CL168
should be set
to the output
mode)CL168
Not used
out
201
L3 VCR[7]/
AVPP[15]
R component input/
Cr component input/
GPIO
Cr component input/
GPIO
Input of the video data for captur-
ing. Common terminal with GPIO.
Input of GPIO after a reset.
ing. Common terminal with GPIO.
Input of GPIO after a reset.
N.C. (The pin
should be set
to the output
mode)CL167
should be set
to the output
mode)CL167
Not used
out
107
H2 VCVSYNC
/
VCVSYNC
#
VCVSYNC
#
Vertical synchro-
nous signal input
nous signal input
Synchronous signal input for cap-
turing. The polarity is programma-
ble.
turing. The polarity is programma-
ble.
Low
Not used
in
pin
No.
pin
assign
ment
Name of
the CPU
the CPU
terminal
VDE
VDD
Signal name
of the CPU
(IC3) on the
main board
Purpose of the signal
I/O
23
KX-PX1EX
207
U3 VDB/CX/
[0]/
AVPP[32]
AVPP[32]
B component output/
C component out-
put/Cb component
output/GPIO
C component out-
put/Cb component
output/GPIO
In the 16-bit YC mode, the Cb
component and the Cr compo-
nent outputs are produced in the
dime division system/Common
terminal with GPIO
component and the Cr compo-
nent outputs are produced in the
dime division system/Common
terminal with GPIO
Head Data1
VDB[0]
VDB[0]
Head Data1
out
18
V1 VDB/CX/
[1]/
AVPP[33]
AVPP[33]
B component output/
C component out-
put/Cb component
output/GPIO
C component out-
put/Cb component
output/GPIO
In the 16-bit YC mode, the Cb
component and the Cr compo-
nent outputs are produced in the
dime division system/Common
terminal with GPIO
component and the Cr compo-
nent outputs are produced in the
dime division system/Common
terminal with GPIO
Head Data2
VDB[1]
VDB[1]
Head Data2
out
117
V2 VDB/CX/
[2]/
AVPP[34]
AVPP[34]
B component output/
C component out-
put/Cb component
output/GPIO
C component out-
put/Cb component
output/GPIO
In the 16-bit YC mode, the Cb
component and the Cr compo-
nent outputs are produced in the
dime division system/Common
terminal with GPIO
component and the Cr compo-
nent outputs are produced in the
dime division system/Common
terminal with GPIO
Head Data3
VDB[2]
VDB[2]
Head Data3
out
208
V3 VDB/CX/
[3]/
AVPP[35]
AVPP[35]
B component output/
C component out-
put/Cb component
output/GPIO
C component out-
put/Cb component
output/GPIO
In the 16-bit YC mode, the Cb
component and the Cr compo-
nent outputs are produced in the
dime division system/Common
terminal with GPIO
component and the Cr compo-
nent outputs are produced in the
dime division system/Common
terminal with GPIO
Head Data4
VDB[3]
VDB[3]
Head Data4
out
291
V4 VDB/CX/
[4]/
AVPP[36]
AVPP[36]
B component output/
C component out-
put/Cb component
output/GPIO
C component out-
put/Cb component
output/GPIO
In the 16-bit YC mode, the Cb
component and the Cr compo-
nent outputs are produced in the
dime division system/Common
terminal with GPIO
component and the Cr compo-
nent outputs are produced in the
dime division system/Common
terminal with GPIO
Head Data5
VDB[4]
VDB[4]
Head Data5
out
366
V5 VDB/CX/
[5]/
AVPP[37]
AVPP[37]
B component output/
C component out-
put/Cb component
output/GPIO
C component out-
put/Cb component
output/GPIO
In the 16-bit YC mode, the Cb
component and the Cr compo-
nent outputs are produced in the
dime division system/Common
terminal with GPIO
component and the Cr compo-
nent outputs are produced in the
dime division system/Common
terminal with GPIO
Head Data6
VDB[5]
VDB[5]
Head Data6
out
19
W1 VDB/CX/
[6]/
AVPP[38]
AVPP[38]
B component output/
C component out-
put/Cb component
output/GPIO
C component out-
put/Cb component
output/GPIO
In the 16-bit YC mode, the Cb
component and the Cr compo-
nent outputs are produced in the
dime division system/Common
terminal with GPIO
component and the Cr compo-
nent outputs are produced in the
dime division system/Common
terminal with GPIO
Head Data7
VDB[6]
VDB[6]
Head Data7
out
118
W2 VDB/CX/
[7]/
AVPP[39]
AVPP[39]
B component output/
C component out-
put/Cb component
output/GPIO
C component out-
put/Cb component
output/GPIO
In the 16-bit YC mode, the Cb
component and the Cr compo-
nent outputs are produced in the
dime division system/Common
terminal with GPIO
component and the Cr compo-
nent outputs are produced in the
dime division system/Common
terminal with GPIO
Head Data8
VDB[7]
VDB[7]
Head Data8
out
209
W3 VDCLK-
OUT
Display pixel clock
output
output
The Pixel data output is produced
in sync with this signal
in sync with this signal
Head_
VDCLK
VDCLK
For making Head Data
Clock
For generating the HEAD
clock
Clock
For generating the HEAD
clock
out
30
AF5 VDD
1.4V
1.4v
1.4v
59
V26 VDD
1.4V
1.4v
1.4v
97
A5 VDD
1.4V
1.4v
1.4v
104
E2 VDD
1.4V
1.4v
1.4v
105
F2 VDD
1.4V
1.4v
1.4v
199
J3 VDD 1.4V
1.4v
1.4v
210
Y3 VDD
1.4V
1.4v
1.4v
219
AD8 VDD
1.4V
1.4v
1.4v
275
C5 VDD
1.4V
1.4v
1.4v
339
D18 VDD
1.4V
1.4v
1.4v
377
AB12 VDD
1.4V
1.4v
1.4v
378
AB13 VDD
1.4V
1.4v
1.4v
383
AB18 VDD
1.4V
1.4v
1.4v
387
AB22 VDD
1.4V
1.4v
1.4v
390
W22 VDD
1.4V
1.4v
1.4v
391
V22 VDD
1.4V
1.4v
1.4v
404
E22 VDD
1.4V
1.4v
1.4v
407
E19 VDD
1.4V
1.4v
1.4v
417
E9 VDD
1.4V
1.4v
1.4v
21
AA1 VDE
3.3V
3.3v
3.3v
121
AB2 VDE
3.3V
3.3v
3.3v
152
Y25 VDE
3.3V
3.3v
3.3v
194
D3 VDE
3.3V
3.3v
3.3v
pin
No.
pin
assign
ment
Name of
the CPU
the CPU
terminal
VDE
VDD
Signal name
of the CPU
(IC3) on the
main board
Purpose of the signal
I/O
24
KX-PX1EX
196
F3 VDE
3.3V
3.3v
3.3v
262
C18 VDE
3.3V
3.3v
3.3v
274
C6 VDE
3.3V
3.3v
3.3v
277
D4 VDE
3.3V
3.3v
3.3v
282
J4 VDE
3.3V
3.3v
3.3v
284
L4 VDE
3.3V
3.3v
3.3v
286
N4 VDE
3.3V
3.3v
3.3v
296
AC4 VDE
3.3V
3.3v
3.3v
298
AC6 VDE
3.3V
3.3v
3.3v
300
AC8 VDE
3.3V
3.3v
3.3v
302
AC10 VDE 3.3V
3.3v
3.3v
310
AC18 VDE 3.3V
3.3v
3.3v
314
AC22 VDE 3.3V
3.3v
3.3v
323
R23 VDE
3.3V
3.3v
3.3v
336
D21 VDE
3.3V
3.3v
3.3v
341
D16 VDE
3.3V
3.3v
3.3v
343
D14 VDE
3.3V
3.3v
3.3v
363
R5 VDE
3.3V
3.3v
3.3v
365
U5 VDE
3.3V
3.3v
3.3v
379
AB14 VDE
3.3V
3.3v
3.3v
381
AB16 VDE
3.3V
3.3v
3.3v
385
AB20 VDE
3.3V
3.3v
3.3v
392
U22 VDE
3.3V
3.3v
3.3v
396
N22 VDE
3.3V
3.3v
3.3v
398
L22 VDE
3.3V
3.3v
3.3v
400
J22 VDE
3.3V
3.3v
3.3v
402
G22 VDE
3.3V
3.3v
3.3v
413
E13 VDE
3.3V
3.3v
3.3v
415
E11 VDE
3.3V
3.3v
3.3v
205
R3 VDG/Y/
X[0]
G component out-
put/Y component
output/YC multiplex
output
put/Y component
output/YC multiplex
output
Video data output for display
Head Data9
VDG[0]
VDG[0]
Head Data9
out
16
T1 VDG/Y/
X[1]
G component out-
put/Y component
output/YC multiplex
output
put/Y component
output/YC multiplex
output
Video data output for display
Head Data10
VDG[1]
VDG[1]
Head Data10
out
115
T2 VDG/Y/
X[2]
G component out-
put/Y component
output/YC multiplex
output
put/Y component
output/YC multiplex
output
Video data output for display
VDG[2] Head//
LAT#
LAT#
For making Head Data
Latch
Latch
out
206
T3 VDG/Y/
X[3]
G component out-
put/Y component
output/YC multiplex
output
put/Y component
output/YC multiplex
output
Video data output for display
VDG[ ] Head//
STB#
STB#
For making Head Data
Strobe
Strobe
out
289
T4 VDG/Y/
X[4]
G component out-
put/Y component
output/YC multiplex
output
put/Y component
output/YC multiplex
output
Video data output for display
VDG[ ] Head//
CLK
CLK
For making Head Data
transfer Clock
transfer Clock
out
364
T5 VDG/Y/
X[5]
G component out-
put/Y component
output/YC multiplex
output
put/Y component
output/YC multiplex
output
Video data output for display
N.C.
Not used
out
17
U1 VDG/Y/
X[6]
G component out-
put/Y component
output/YC multiplex
output
put/Y component
output/YC multiplex
output
Video data output for display
N.C.
Not used
out
116
U2 VDG/Y/
X[7]
G component out-
put/Y component
output/YC multiplex
output
put/Y component
output/YC multiplex
output
Video data output for display
N.C.
Not used
out
292
W4 VDHSYNC
Horizontal
synchro-
nous signal output
Synchronous signal output for
display
display
Not use
Not used
out
pin
No.
pin
assign
ment
Name of
the CPU
the CPU
terminal
VDE
VDD
Signal name
of the CPU
(IC3) on the
main board
Purpose of the signal
I/O
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