Panasonic KX-PX1EX Service Manual ▷ View online
13
KX-PX1EX
(D) Printing position
• The thermal head is further lowered to be pressed on the capstan roller so that the head recording member, the ink sheet, and
the paper are pressed together.
• The capstan roller is rotated in reverse to start recording the image signals.
First, Yellow is printed. Magenta, Cyan, and Over Coat are recorded by repeating steps (C) and (D) sequentially. After that, the
system goes to the next mode.
system goes to the next mode.
(E) Ejection position
• The recording paper is sent to the outside of the printer by the rotation force of the pick up roller and the paper ejection is com-
pleted. The mode then goes to (A) stand-by position and the printing operation is finished.
14
KX-PX1EX
4.5.
Microcomputer I/O table
4.5.1.
IC3 CPU (Main)
pin
No.
pin
assign
ment
Name of
the CPU
the CPU
terminal
VDE
VDD
Signal name
of the CPU
(IC3) on the
main board
Purpose of the signal
I/O
253
F24
A[10]
Local Bus Address
Local bus address signal
CPA[10]
Address for ROM
out
332
F23
A[11]
Local Bus Address
Local bus address signal
CPA[11]
Address for ROM
out
403
F22
A[12]
Local Bus Address
Local bus address signal
CPA[12]
Address for ROM
out
72
E26
A[13]
Local Bus Address
Local bus address signal
CPA[13]
Address for ROM
out
167
E25
A[14]
Local Bus Address
Local bus address signal
CPA[14]
Address for ROM
out
254
E24
A[15]
Local Bus Address
Local bus address signal
CPA[15]
Address for ROM
out
168
D25
A[16]
Local Bus Address
Local bus address signal
CPA[16]
Address for ROM
out
255
D24
A[17]
Local Bus Address
Local bus address signal
CPA[17]
Address for ROM
out
334
D23
A[18]
Local Bus Address
Local bus address signal
CPA[18]
Address for ROM
out
257
C23
A[19]
Local Bus Address
Local bus address signal
CPA[19]
Address for ROM
out
251
H24
A[2]
Local Bus Address
Local bus address signal
CPA[2]
Address for ROM
out
335
D22
A[20]
Local Bus Address
Local bus address signal
CPA[20]
Address for ROM
out
258
C22
A[21]
Local Bus Address
Local bus address signal
CPA[21]
Address for ROM
out
173
B22 A[22]
Local
Bus
Address
Local bus address signal
N.C.
Not used
out
80
A22 A[23]
Local
Bus
Address
Local bus address signal
N.C.
Not used
out
259
C21 A[24]
Local
Bus
Address
Local bus address signal
N.C.
Not used
out
174
B21 A[25]
Local
Bus
Address
Local bus address signal
N.C.
Not used
out
81
A21 A[26]
Local
Bus
Address
Local bus address signal
N.C.
Not used
out
406
E20 A[27]
Local
Bus
Address
Local bus address signal
N.C.
Not used
out
337
D20 A[28]
Local
Bus
Address
Local bus address signal
N.C.
Not used
out
260
C20 A[29]
Local
Bus
Address
Local bus address signal
N.C.
Not used
out
330
H23
A[3]
Local Bus Address
Local bus address signal
CPA[3]
Address for ROM
out
175
B20 A[30]
Local
Bus
Address
Local bus address signal
N.C.
Not used
out
177
B18 A[31]
Local
Bus
Address
Local bus address signal
N.C.
Not used
out
401
H22
A[4]
Local Bus Address
Local bus address signal
CPA[4]
Address for ROM
out
70
G26
A[5]
Local Bus Address
Local bus address signal
CPA[5]
Address for ROM
out
165
G25
A[6]
Local Bus Address
Local bus address signal
CPA[6]
Address for ROM
out
252
G24
A[7]
Local Bus Address
Local bus address signal
CPA[7]
Address for ROM
out
71
F26
A[8]
Local Bus Address
Local bus address signal
CPA[8]
Address for ROM
out
166
F25
A[9]
Local Bus Address
Local bus address signal
CPA[9]
Address for ROM
out
369
AA5
BCKI
Bit clock input
Input the bit clock used for audio
input
input
Low GND
Not used
in
295
AB4 BCKO/
MCLK
Bit clock output
Bit clock output for audio input
and output
and output
N.C.
Not used
out
69
H26 BCLKO Bus ClocK Out
(unusable)
Terminal that is prohibited from
being used
being used
N.C.
Not used
out
68
J26 BE[0]
Byte
Enable
BE[0]
→D[31:24]
When RSTOUT# is asserted, the
value of BE[0] is reflected to
LGCR.BED.
value of BE[0] is reflected to
LGCR.BED.
10k
Pull_Down
Pull_Down
Not used
in/out
163
J25 BE[1]
BE[1]
→D[23:16]
N.C. CL5
Not used
out
250
J24 BE[2]
BE[2]
→A[1]
BE[2]
→D[15:08]
CPA[1]
Address for ROM
out
164
H25 BE[3]
BE[3]
→A[0]
BE[3]
→D[07:00]
N.C. CL6
Not used
out
264
C16
BGNT#
Bus GraNT
This is a signal to indicate that the
local bus is open.
local bus is open.
N.C.
Not used
out
261
C19
BREQ#
Bus REQuest
This is a signal to input the
request to open the bus from the
bus master device.
request to open the bus from the
bus master device.
High 33k
Pul_UP
Pul_UP
Not used
in
85
A17
BS#
Bus cycle Start
Indicate the start of the bus cycle N.C.
Not used
out
84
A18 BSTACK# BurST ACKnowl-
edge
Input and output the burst trans-
fer permission
fer permission
High 33k
Pul_UP
Pul_UP
Not used
out
83
A19
BSTREQ# BurST REQuest
Input and output the burst trans-
fer request for the signal
fer request for the signal
High 33k
Pul_UP
Pul_UP
Not used
in
154
V25
CLKIN
CLocK INput
Supply the clock from the outside 64MHz(SSCG
)
CPU clock (64Mhz)
in
319
W23
CMODE[0] Clock MODE
Determine the operating fre-
quency ratio of the each part
inside LSI
quency ratio of the each part
inside LSI
High
Internal frequency mode
setting (H)
setting (H)
in
15
KX-PX1EX
240
W24 CMODE[1]
Clock
MODE
Determine the operating fre-
quency ratio of the each part
inside LSI
quency ratio of the each part
inside LSI
High
Internal frequency mode
setting (H)
setting (H)
in
153
W25 CMODE[2]
Clock
MODE
Determine the operating fre-
quency ratio of the each part
inside LSI
quency ratio of the each part
inside LSI
Low
Internal frequency mode
setting (L)
setting (L)
in
58
W26 CMODE[3] Clock
MODE
Determine the operating fre-
quency ratio of the each part
inside LSI
quency ratio of the each part
inside LSI
Low
Internal frequency mode
setting (L)
setting (L)
in
181
B14
CPUHOLD CPU Hold
Determine the operating fre-
quency ratio of the each part
inside LSI
quency ratio of the each part
inside LSI
N.C.
Not used
out
179
B16
CS#[0]
Chip Select
Selection signal to select the
slave device
slave device
ROMCS# :IC5
FROM Select
FROM Select
Selection for ROM
out
86
A16
CS#[1]
Chip Select
Selection signal to select the
slave device
slave device
N.C. CL10
Not used
out
411
E15
CS#[2]
Chip Select
Selection signal to select the
slave device
slave device
N.C. CL9
Not used
out
342
D15
CS#[3]
Chip Select
Selection signal to select the
slave device
slave device
N.C. CL8
Not used
out
265
C15 CS#[4]/
IRQ#[4]
Chip Select/Inter-
rupt ReQuest
rupt ReQuest
Selection signal to select the
device/interruption input signal
device/interruption input signal
N.C. 10k_
Pull_UP
Pull_UP
Not used
in
180
B15 CS#[5]/
IRQ#[5]
Chip Select/Inter-
rupt ReQuest
rupt ReQuest
Selection signal to select the
device/interruption input signal
device/interruption input signal
VBUS_F_DC
T# ,CPU
PP15
T# ,CPU
PP15
Interruption at USB_F
Vbus detection
Vbus detection
in
87
A15 CS#[6]/
IRQ#[6]
Chip Select/Inter-
rupt ReQuest
rupt ReQuest
Selection signal to select the
device/interruption input signal
device/interruption input signal
78k_IRQ0#
P40
P40
Interrupt signal from
Mechanical CPU
Mechanical CPU
in
266
C14 CS#[7]/
IRQ#[7]
Chip Select/Inter-
rupt ReQuest
rupt ReQuest
Selection signal to select the
device/interruption input signal
device/interruption input signal
78k_IRQ1#
P41
P41
Interrupt signal from
Mechanical CPU
Mechanical CPU
in
242
U24
D[0]
Local Bus Data
Local bus data
N.C.
Not used
I/O
155
U25
D[1]
Local Bus Data
Local bus data
N.C.
Not used
I/O
62
R26
D[10]
Local Bus Data
Local bus data
N.C.
Not used
I/O
395
P22
D[11]
Local Bus Data
Local bus data
N.C.
Not used
I/O
324
P23
D[12]
Local Bus Data
Local bus data
N.C.
Not used
I/O
245
P24
D[13]
Local Bus Data
Local bus data
N.C.
Not used
I/O
158
P25
D[14]
Local Bus Data
Local bus data
N.C.
Not used
I/O
63
P26
D[15]
Local Bus Data
Local bus data
N.C.
Not used
I/O
64
N26
D[16]
Local Bus Data
Local bus data
CPD[0]
Data for ROM
I/O
159
N25
D[17]
Local Bus Data
Local bus data
CPD[1]
Data for ROM
I/O
246
N24
D[18]
Local Bus Data
Local bus data
CPD[2]
Data for ROM
I/O
65
M26
D[19]
Local Bus Data
Local bus data
CPD[3]
Data for ROM
I/O
60
U26
D[2]
Local Bus Data
Local bus data
N.C.
Not used
I/O
160
M25
D[20]
Local Bus Data
Local bus data
CPD[4]
Data for ROM
I/O
247
M24
D[21]
Local Bus Data
Local bus data
CPD[5]
Data for ROM
I/O
326
M23
D[22]
Local Bus Data
Local bus data
CPD[6]
Data for ROM
I/O
397
M22
D[23]
Local Bus Data
Local bus data
CPD[7]
Data for ROM
I/O
66
L26
D[24]
Local Bus Data
Local bus data
CPD[8]
Data for ROM
I/O
161
L25
D[25]
Local Bus Data
Local bus data
CPD[9]
Data for ROM
I/O
248
L24
D[26]
Local Bus Data
Local bus data
CPD[10]
Data for ROM
I/O
67
K26
D[27]
Local Bus Data
Local bus data
CPD[11]
Data for ROM
I/O
162
K25
D[28]
Local Bus Data
Local bus data
CPD[12]
Data for ROM
I/O
249
K24
D[29]
Local Bus Data
Local bus data
CPD[13]
Data for ROM
I/O
393
T22
D[3]
Local Bus Data
Local bus data
N.C.
Not used
I/O
328
K23
D[30]
Local Bus Data
Local bus data
CPD[14]
Data for ROM
I/O
399
K22
D[31]
Local Bus Data
Local bus data
CPD[15]
Data for ROM
I/O
322
T23
D[4]
Local Bus Data
Local bus data
N.C.
Not used
I/O
243
T24
D[5]
Local Bus Data
Local bus data
N.C.
Not used
I/O
156
T25
D[6]
Local Bus Data
Local bus data
N.C.
Not used
I/O
61
T26
D[7]
Local Bus Data
Local bus data
N.C.
Not used
I/O
244
R24
D[8]
Local Bus Data
Local bus data
N.C.
Not used
I/O
157
R25
D[9]
Local Bus Data
Local bus data
N.C.
Not used
I/O
38
AF13 DA[0]
sDram
multiplexed
Address
Multiplex address for SDRAM
SDA[0]
Address for SDRAM
out
39
AF14 DA[1]
sDram
multiplexed
Address
Multiplex address for SDRAM
SDA[1]
Address for SDRAM
out
pin
No.
pin
assign
ment
Name of
the CPU
the CPU
terminal
VDE
VDD
Signal name
of the CPU
(IC3) on the
main board
Purpose of the signal
I/O
16
KX-PX1EX
138
AE16 DA[10]
sDram
multiplexed
Address
Multiplex address for SDRAM
SDA[10]
Address for SDRAM
out
139
AE17 DA[11]
sDram
multiplexed
Address
Multiplex address for SDRAM
SDA[11]
Address for SDRAM
out
228
AD17 DA[12]
sDram
multiplexed
Address
Multiplex address for SDRAM
N.C.
Not used
out
136
AE14 DA[2]
sDram
multiplexed
Address
Multiplex address for SDRAM
SDA[2]
Address for SDRAM
out
225
AD14 DA[3]
sDram
multiplexed
Address
Multiplex address for SDRAM
SDA[3]
Address for SDRAM
out
40
AF15 DA[4]
sDram
multiplexed
Address
Multiplex address for SDRAM
SDA[4]
Address for SDRAM
out
137
AE15 DA[5]
sDram
multiplexed
Address
Multiplex address for SDRAM
SDA[5]
Address for SDRAM
out
226
AD15 DA[6]
sDram
multiplexed
Address
Multiplex address for SDRAM
SDA[6]
Address for SDRAM
out
307
AC15 DA[7] sDram
multiplexed
Address
Multiplex address for SDRAM
SDA[7]
Address for SDRAM
out
380
AB15 DA[8]
sDram
multiplexed
Address
Multiplex address for SDRAM
SDA[8]
Address for SDRAM
out
41
AF16 DA[9]
sDram
multiplexed
Address
Multiplex address for SDRAM
SDA[9]
Address for SDRAM
out
227
AD16 DBA[0]
sDram
Bank
Address
Bank address output is produced SDBA0
SDRAM Bank Address
out
42
AF17 DBA[1]
sDram
Bank
Address
Bank address output is produced SDBA1
SDRAM Bank Address
out
35
AF10 DCAS#
sDram
Column
Address Strobe
Column address strobe signal
SDCAS#
SDRAM Column Address
Strobe
CAS signal for SDRAM
Strobe
CAS signal for SDRAM
out
309
AC17 DCKE sDram
ClocK
Enable
Clock Enable signal
SDCKE
SDRAM Clock Enable
Clock enable signal for
SDRAM
Clock enable signal for
SDRAM
out
304
AC12 DCLK
sDram CLocK
SDRAM clock
SDCLK
SDRAM Clock
out
134
AE12 DCLKFB FeedBack
for
sDram
CLocK
Adjust the phase of DCLK Feed-
back input
back input
SDCLKFB
Feedback for SDRAM
Clock Adjust the phase of
DCLK Feedback input
Clock Adjust the phase of
DCLK Feedback input
in
222
AD11 DCS#[0]
sDram Chip Select
Selection of SDRAM
SDCS0#
SDRAM Chip Select
out
133
AE11 DCS#[1]
sDram Chip Select
Selection of SDRAM
N.C.
Not used
36
AF11 DCS#[2]
sDram Chip Select
Exclusively for connecting 168-
pin registered DIMM
pin registered DIMM
N.C.
Not used
out
224
AD13 DCS#[3]
sDram Chip Select
Exclusively for connecting 168-
pin registered DIMM
pin registered DIMM
N.C.
Not used
out
217
AD6
DDQ[0]
sDram Data
SDRAM data
SDD[0]
SDRAM Data
I/O
128
AE6
DDQ[1]
sDram Data
SDRAM data
SDD[1]
SDRAM Data
I/O
374
AB9
DDQ[10]
sDram Data
SDRAM data
SDD[10]
SDRAM Data
I/O
301
AC9
DDQ[11]
sDram Data
SDRAM data
SDD[11]
SDRAM Data
I/O
220
AD9
DDQ[12]
sDram Data
SDRAM data
SDD[12]
SDRAM Data
I/O
131
AE9
DDQ[13]
sDram Data
SDRAM data
SDD[13]
SDRAM Data
I/O
34
AF9
DDQ[14]
sDram Data
SDRAM data
SDD[14]
SDRAM Data
I/O
221
AD10 DDQ[15]
sDram Data
SDRAM data
SDD[15]
SDRAM Data
I/O
140
AE18 DDQ[16]
sDram Data
SDRAM data
SDD[16]
SDRAM Data
I/O
44
AF19
DDQ[17]
sDram Data
SDRAM data
SDD[17]
SDRAM Data
I/O
141
AE19 DDQ[18]
sDram Data
SDRAM data
SDD[18]
SDRAM Data
I/O
230
AD19 DDQ[19]
sDram Data
SDRAM data
SDD[19]
SDRAM Data
I/O
31
AF6
DDQ[2]
sDram Data
SDRAM data
SDD[2]
SDRAM Data
I/O
311
AC19 DDQ[20]
sDram Data
SDRAM data
SDD[20]
SDRAM Data
I/O
384
AB19 DDQ[21]
sDram Data
SDRAM data
SDD[21]
SDRAM Data
I/O
45
AF20
DDQ[22]
sDram Data
SDRAM data
SDD[22]
SDRAM Data
I/O
142
AE20 DDQ[23]
sDram Data
SDRAM data
SDD[23]
SDRAM Data
I/O
231
AD20 DDQ[24]
sDram Data
SDRAM data
SDD[24]
SDRAM Data
I/O
46
AF21
DDQ[25]
sDram Data
SDRAM data
SDD[25]
SDRAM Data
I/O
143
AE21 DDQ[26]
sDram Data
SDRAM data
SDD[26]
SDRAM Data
I/O
232
AD21 DDQ[27]
sDram Data
SDRAM data
SDD[27]
SDRAM Data
I/O
313
AC21 DDQ[28]
sDram Data
SDRAM data
SDD[28]
SDRAM Data
I/O
386
AB21 DDQ[29]
sDram Data
SDRAM data
SDD[29]
SDRAM Data
I/O
372
AB7
DDQ[3]
sDram Data
SDRAM data
SDD[3]
SDRAM Data
I/O
pin
No.
pin
assign
ment
Name of
the CPU
the CPU
terminal
VDE
VDD
Signal name
of the CPU
(IC3) on the
main board
Purpose of the signal
I/O
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