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Model
KV-S2087 (serv.man2)
Pages
127
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19.7 MB
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Service Manual
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kv-s2087-sm2.pdf
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Panasonic KV-S2087 (serv.man2) Service Manual ▷ View online

89
F63 (Back-side
black level error)
53
00
00
00 1. Pixel data from Optical Unit Back
or image processing circuit
has some problems.
1.Check if the White Standard Sheet is not dirty
and not peeled, then is stuck properly.
2.Refer to the above 3rd item on the F62.
F80 (Double Feed
Detector
adjustment error)
60
00
00
00 1. Double Feed Detector (G) does
not work, properly.
Refer to the 5th item on Classified Code U23.
2. Double Feed Detector (R) does
not work, properly.
Refer to the 6th item on Classified Code U23.
F90 
(Sub-Processor Error)
9E
xx
xx
xx Processor error in the Gate Array 
(IC32/IC40)
1. Check the soldering condition of the follow-
ing part and of their surrounding circuits on
the Main Board.
a. Gate Array
          (ST3:00 IC32/ST3:01 IC40)
2. Replace faulty parts or boards.
Error Code
ST1 ST2 ST3 ST4
Possible Cause
Check Point
Remarks
90
12 Block Diagram
12.1. Block Diagram-1 (Image Processing)
On this system, the CPU (IC5) controls operation of the ASICs (IC32,IC40), FPGA (IC19,IC40),the Sensors (Paper Sensor and oth-
ers), and the Motors (Paper Feed and others).
Motor pulse signals for conveying paper (Conveyor Motor) are provided from the ASIC (IC32).
On the other hand, motor pulse signals for the other motors are provided from the CPU (IC5) and FPGA (IC47). 
The FPGA (IC19) requires SDRAM (IC20) as the buffer memory.
The ASIC (IC32) requires SDRAM (IC27, IC28, IC29, IC30) to store and output pre-processed and post-processed image data for
the front side.
The FPGA (IC25) requires SDRAM (IC26) as the buffer memory.
The ASIC (IC40) requires SDRAM (IC34, IC35, IC36, IC37) to store and output pre-processed and post-processed image data for
the back side.
In order to perform duplex scanning, this scanner has 2 CISs (CIS(F), CIS(B)) to scan image signals for the front and back sides.
The FPGA (IC19) receive front image signals from CIS(F), and then performs the line correction for them. After that, the ASIC
(IC32) pre-processes them.
The FPGA (IC25) receive front image signals from CIS(B), and then performs the line correction for them. After that, the ASIC
(IC40) pre-processes them.
 (Pre-process means shading correction and dpi transformation)
After finishing pre-processing, the ASIC (IC32, IC40) post-process the data into binary or compressed data.
Then the ASIC (IC32, IC40) sends the data which performed post-processing to USB Controller (IC42) via FPGA (IC47). And ASIC
(IC32, IC40) sends the data which relayed FPGA (IC47) and performed post-processing to the USB controller (IC42).
The USB controller (IC42) sends data to the PC via USB interface.
* Post-process means binary processing (simple binary, auto binary, dither, error diffusion), color, and gray scale image processing
(MTF, Color Correction, Gamma Correction etc.).
×
×
×
×
×
B
IC16
IC22
91
12.2. Block Diagram-2 (Board)
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92
12.3. Explanation of Connector
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