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CM2054C

Ise Electronics Corporation

:Anode & Grid Assignment

G1

Sheet 5/5

NL

(F2)

F1,F2:Filament   G1-G10:Grid

S1-S24:Anode   NP:No Pin   NL:No Lead

PIN ASSIGNMENT

Pin No.

Assignment

F2 NP NL S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2

Pin No.

Assignment

NL NL NL NL G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 NL NP F1 NL

(F1)

S1

G2

G3

G4

G5

G6

G7

G8

G9

G10

S1
S2
S3
S4
S5
S6
S7
S8
S9

S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24

S1

LFE

S3
S4
SL
S6
S7

SBL

S9

S10

SR

S12
S13
SBR
S15
S16

R

S18
S19

C

S21
S22

L

NIGHT

S1
S2
S3
S4
S5
S6
S7

S10
S11
S12
S13
S14
S15
S16

PRESET

SLEEP
MULTI

S1
S2
S3
S4
S5
S6
S7
S8
S9

S10
S11
S12
S13
S14
S15
S16

dB
ST

MEM
KHz
MHz

LOGIC 7

C
M

S1
S2
S3
S4
S5
S6
S7
S8
S9

S10
S11
S12
S13
S14
S15
S16

TUNED

VMAx

N
F

S1
S2
S3
S4
S5
S6
S7
S8
S9

S10
S11
S12
S13
S14
S15
S16

TA

AUTO

DSP

S1
S2
S3
S4
S5
S6
S7
S8
S9

S10
S11
S12
S13
S14
S15
S16

RDS
OSD

S1
S2
S3
S4
S5
S6
S7
S8
S9

S10
S11
S12
S13
S14
S15
S16
S17

ANALOG

3

ST

S1
S2
S3
S4
S5
S6
S7
S8
S9

S10
S11
S12
S13
S14
S15
S16

COAX

1
2
3

S1
S2
S3
S4
S5
S6
S7
S8
S9

S10
S11
S12
S13
S14
S15
S16

OPT

1
2
3

S1
S2
S3
S4
S5
S6
S7
S8
S9

S10
S11
S12
S13
S14
S15
S16

HDCD

MP3
PCM

  PL

D

D

DTS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

1,12,23

+VD1

-

Digital Power supply. Normally +2.5v

2,13,24

DGND

-

Digital Ground

3

AUD3

O

SPDIF transmitter output/Digital audio output(N.C)

4

WR

I

Host write strobe pin(connected to GND with an external resistor)

5

RD

I

Host parallel output enable pin(pulled up with an external resistor)

6 CS_DA I SPI Serial data input pin

7

CS_CK

I

Serial control clock input pin

8

EMAD7

I/O

9

EMAD6

I/O

10

EMAD5

I/O

11

EMAD4

I/O

Serial data IN/OUTPUT pins(pulled up with an external resistor)

14

EMAD3

I/O

15

EMAD2

I/O

16

EMAD1

I/O

17

EMAD0

I/O

18

CS_CE

I

Host parallel chip select pin

19

SCDIO(AK_DOUT)

O

Serial control port data ouput pin

20

INTREQ

O

Control port interrupt request output pin

21

EXTMEM

I/O

External Memory Chip Selector(pulled up with an external resistor)

22

SDATAN1(SDI)

I

PCM audio data input number 1 pin

25

SCLKN1(BICK)

I

PCM audio input bit clock pin

26

LRCLKN1(LRCK)

I

PCM audio input sample rate clock pin

27

CMPDAT(SDI)

I

PCM audio data input number 2 pin

28

CMPCLK(BICK)

I

PCM audio input bit clock pin

29

CREQ(LRCK)

I

PCM audio input sample rate clock pin

30

CLKIN(XIN)

I

Master clock input(used external clock)

31

CLKSEL(GND)

I

DSP clock mode select pin: connect the GND

32

FILT1

Connects to an external filter for the on-chip phase-locked loop

33

FILT1

Connects to an external filter for the on-chip phase-locked loop

34

+2.5V

-

Analog Power supply for clock generator . Normally +2.5V

35

AGND

-

Analog ground supply for clock generator PLL.

36

RESET(CS_RST)

I

Master reset input pin

37

DBDATA

-

Reserved pin and should be pulled up with an external resistor.

38

DBCLK

-

Reserved pin and should be pulled up with an external resistor.

39

AUD2(SDO2)

O

PCM multi-format digital-audio data ouput2 pin

40

AUD1(SDO1)

O

PCM multi-format digital-audio data ouput1 pin

41

AUD0(SDO0)

O

PCM multi-format digital-audio data ouput0 pin

42

LRCLK

I

Audio output sample rate clock pin

43

SCLK(BICK)

I

Audio ouput bit clock pin

44

MCLK

I

Audio master clock output pin

CMPDAT
SDATAN2

CMPCLK
SCLKN2

CMPREQ
LRCLKN2

SCLKN1
STCCLK2

LRCLKN1

SDATAN1

CLKIN

CLKSEL

FILTD

FILTS

VA

AGND

DGND(3:1)

VD(3:1)

XMT95

AUDA

LRCLK

SCLK

MCLK

DC

DD

EXTMEM.

GPIO8

A800T

INTERQ

A1,

SCDIN

A0,

SCCLK

CS

STC

Parallel or Serial Host Interface

RESET

SCDIO,

SCDOUT,

PSEL,

GPIO9

WR,

DR,

EMWR,

GPIO10

RD,

R/W,

EMOE,

GPIO11

DATA7:0,

EMAD7:0,

GPIO7:0

Compressed

Data Input

Interface

RAM

Program

Memory

ROM

Program

Memory

RAM

Data

Memory

RAM

Output

Buffer

Output

Formatter

ROM

Data

Memory

PLL

Clock Manager

RAM Input

Buffer

24-Bit

DSP Processing

Digital

Audio

Input

Interface

Framer

Shifter

Input

Buffer

Controller

The LC74763 and LC74763M are on-screen display
CMOS LSIs that superimpose text and low-level
graphics onto a TV screen (video signal) under the
control of a microcontroller. The display characters
have a 12 by 18 dots structure, and 128 characters are
provided.

• Display structure: 12 lines by 24 characters (up to 288

characters)

• Maximum character display: Up to 288 characters
• Character configuration: 12 (W) by 18 (H) dots

structure

• Number of characters: 128 characters (128 plus space

2 fonts)

• Character sizes: Three sizes (normal, double, and

triple sizes)

• Display starting positions: 64 horizontal and 64

vertical locations

• Reverse video function: Characters can be inverted on

a per character basis.

• Flashing types: Two types with periods of 0.5 and 1.0

second on a per character basis (duty fixed at 50%)

• Background color: One of eight colors (when internal

synchronization used)

• External control input: Serial data input in 8-bit units
• Built-in horizontal/vertical sync separation circuit,

AFC circuit, and synchronization detector

• Video output: Composite video signal output in

NTSC, PAL, PAL-M, PAL-N, PAL60, NTSC4.43, or
SECAM format

unit: mm

unit: mm

[LC74763M]

SANYO: MFP30S

[LC74763]

SANYO: DIP30SD

CMOS IC

Ordering number : 

*

EN5039

32095TH (OT) No. 5039-1/19

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN