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No.

Pin Name

I/O

Function

31

PDN

I

Power-Down Mode Pin

When “L”, the AK4114 is powered-down and reset.

CM0

I

Master Clock Operation Mode 0 Pin in Parallel Mode

CDTO

O

Control Data Output Pin in Serial Mode, IIC= “L”.

32

CAD1

I

Chip Address 1 Pin in Serial Mode, IIC= “H”.

CM1

I

Master Clock Operation Mode 1 Pin in Parallel Mode

CDTI

I

Control Data Input Pin in Serial Mode, IIC= “L”.

33

SDA

I/O

Control Data Pin in Serial Mode, IIC= “H”.

OCKS1

I

Output Clock Select 1 Pin in Parallel Mode

CCLK

I

Control Data Clock Pin in Serial Mode, IIC= “L”

34

SCL

I

Control Data Clock Pin in Serial Mode, IIC= “H”

OCKS0

I

Output Clock Select 0 Pin in Parallel Mode

CSN

I

Chip Select Pin in Serial Mode, IIC=”L”.

35

CAD0

I

Chip Address 0 Pin in Serial Mode, IIC= “H”.

36

INT0

O

Interrupt 0 Pin

37

INT1

O

Interrupt 1 Pin

38

AVDD

I

Analog Power Supply Pin, 3.3V

39

R

-

External Resistor Pin

18k

Ω

 +/-1% resistor should be connected to AVSS externally.

40

VCOM

-

Common Voltage Output Pin

0.47µF capacitor should be connected to AVSS externally.

41

AVSS

I

Analog Ground Pin

42

RX0

I

Receiver Channel 0 Pin (Internal biased pin)

This channel is default in serial mode.

43

NC(AVSS)

I

No Connect

No internal bonding. This pin should be connected to AVSS.

44

RX1

I

Receiver Channel 1 Pin (Internal biased pin)

45

TEST1

I

TEST 1 pin.

This pin should be connected to AVSS.

46

RX2

I

Receiver Channel 2 Pin (Internal biased pin)

47

NC(AVSS)

I

No Connect

No internal bonding. This pin should be connected to AVSS.

48

RX3

I

Receiver Channel 3 Pin (Internal biased pin)

Note 1. All input pins except internal biased pins should not be left floating.

© 2000 Fairchild Semiconductor Corporation

DS005355

www.fairchildsemi.com

August 1984

Revised January 2000

The MM74HC4066 devices are digitally controlled analog
switches utilizing advanced silicon-gate CMOS technology.
These switches have low “ON” resistance and low “OFF”
leakages. They are bidirectional switches, thus any analog
input may be used as an output and visa-versa. Also the
MM74HC4066 switches contain linearization circuitry
which lowers the “ON” resistance and increases switch lin-
earity. The MM74HC4066 devices allow control of up to
12V (peak) analog signals with digital control signals of the
same range. Each switch has its own control input which
disables each switch when LOW. All analog inputs and out-
puts and digital inputs are protected from electrostatic
damage by diodes to V

CC

 and ground.

■

Typical switch enable time: 15 ns

■

Wide analog input voltage range: 0–12V

■

Low “ON” resistance: 30 typ. (MM74HC4066)

■

Low quiescent current: 80 

µ

A maximum (74HC)

■

Matched switch characteristics

■

Individual switch controls

 

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

MM74HC4066M

M14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow

MM74HC4066SJ

M14D

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

MM74HC4066MTC

MTC14

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

MM74HC4066N

N14A

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

L

“OFF”

H

“ON”