Sony CPD-G420 / CPD-G420S / CPD-G520 / GDM-F520 Service Manual ▷ View online
CR1 chassis (E)
9
3-2-2-3. Sub Converter
Fly-back type hard switching
This circuit consists of a control IC IC610 and a Q630 for switching FET.
It provides USB voltage.
D632 and D633 compose a snubber.
Shunt regulator IC680 feeds back the output.
The output voltage is supplied to the USB board and the heater circuit.
3-2-2-4. Main Converter
The Main Converter is a current resonance type converter of separately excited oscillating system.
The resonance frequency is decided by the 5-7 winding inductance of T620 and the resonance capacitor C658.
By turning on/off two MOSFET Q640 and Q641 alternately, the current is fed to the 5-7 winding of T620 to generate the voltage in the
secondary winding.
The output voltage is controlled by detecting the +B output voltage (+ pin of C650) by IC640, and varying the switching frequency of
Q640 and Q641, namely by the frequency modulation system.
As the load becomes heavy, the switching frequency lowers.
The +B2 and (15 V are outputted according to the turn ratio to the winding for +B output.
3-2-2-5. Degauss Circuit
The degauss operation is controlled by the DEGAUSS SW signal from the micro controller.
When the DEGAUSS SW signal goes High, Q611 turns on, and then RY603 (2 contacts) turns on.
When the relay turns on, the current flows to the degauss coil from CN601 through positive characteristic thermistor.
The positive characteristic thermistor increases its resistance value due to heating when the current flows, thus gradually attenuating
the current flowing into the degauss coil.
The DEGAUSS SW signal goes Low about 6 seconds after the degauss started. The RY603 turns off and the degauss operation
finishes.
3-2-2-6. ON/OFF Circuit
It consists of Q652, PH620, and Q610.
When the Power signal is outputted from the micro controller, Q610 turns on to supply Vcc from "Sub Converter" to the "Main
Converter" and "Active Filter Circuit".
3-2-2-7. Standby Voltage Output Circuit
The 2-output series regulator IC652 supplies standby 5 V and 3.3 V.
The 5 V power is outputted normally.
The ON/OFF of 3.3 V power is controlled by the Power signal from the micro controller.
CR1 chassis (E)
10
No
Pin name
I/O
Level
PU/PD [kW]
Power supply
Functional description
for buffer
1
HDF
O
ANALOG
AVDD1/AGND1
Horizontal dynamic focus waveform
(R-strings DAC)
2
DCC2
O
ANALOG
AVDD1/AGND1
Center voltage of 8bit R-String DAC
4.
DA BOARD
4-1. GENERAL
The DA board comprises only the DSP IC inputs and outputs and relevant peripheral applications.
The pin functional description of DA board connector (CN502 on D board) as viewed from the set is substitutable with the D board
circuit description, and here, the DSP functions in the DA board are described.
Arrangement on A side of DA Board :
Vsaw Buffer
(IC1102)
CN1101
DSP
(IC1101)
4-2.
FUNCTION
The DA board provides mainly two functions:
(1) PLL function (alias "Jungle") that receives Hsync from the OSD IC (Sync Processor built in) and outputs HD stably synchronized
with Hsync
(2) DSP function that generates various deflection circuit control waveforms synchronized with Vsync and HFBP and outputs them by
DAC
The functions (1) and (2) are interacted, and the CLK to form waveforms by (2) is generated by (1). Accordingly, internal digital clock
is timing-locked to horizontal deflection.
Also, Vsaw (original waveform to output horizontal deflection) is outputted to the D board through active filter by an external buffer
(OP-AMP) to minimize the noise.
The deflection control waveforms outputted from DSP are classified into mainly three types depending on the kind of DAC.
PWM D/A type : DC only
1bit D/A type : V-period control waveforms, except Vsaw itself
Waveforms generated by filtering 0 V - 3.3 V 1/0 signals in RC. The D range is inevitably 0 V to 3.3 V.
R-Strings D/A : Mainly H-period waveforms. Vsaw belongs to this because of necessary
resolution.
Static DAC that outputs waveforms directly. The voltage range to generate waveforms is 1 V to 2 V. Some H-period waveforms
may be modulated at V-period.
For detailed DSP IC control by the micro controller, refer to the Software Specifications.
The following shows the pin assignment of DSP IC (extracted from NEC Specifications)
CR1 chassis (E)
11
No
Pin name
I/O
Level
PU/PD [kW]
Power supply
Functional description
for buffer
3
XDC
O
ANALOG
AVDD1/AGND1
Dynamic convergence waveform
in X direction
4
AVDD1
-
-
Analog system power supply
(VDD in DAC system)
5-6
TEST0-
I
LVTTL
AVDD1/AGND1
For LSI test
TEST1
Normally connected to GND
7
MOIRE
O
ANALOG
AVDD0/AGND0
Moire control is outputted
(R-strings DAC)
DA internal completion
8
TEST5
→
O
ANALOG
AVDD0/AGND0
Corrected waveform in horizontal phase system,
HSPBL(L)
Lower 5-bit waveform
(R-strings DAC)
DA internal completion
9
HSPBL(H)
O
ANALOG
AVDD0/AGND0
Corrected waveform in horizontal phase system,
Upper 10-bit waveform
(R-strings DAC)
DA internal completion
10
AVDD0
-
-
AVDD0/AGND0
Analog system power supply
(VDD in PLL system)
11
PC2-FIL
I/O
ANALOG
AVDD0/AGND0
External filter for PC2
12
OSC-LIM2 I/O
ANALOG
AVDD0/AGND0
Control current resistor is connected (for VCO2)
13
OSC-REF2 I/O
ANALOG
Reference resistor for VCO2 is connected
14
VCO-FIL
I/O
ANALOG
AVDD0/AGND0
Filter pin for B/G regulator noise reduction
15
PC-ADJ
I/O
-
AVDD0/AGND0
Reference resistor for phase comparator is
connected
16
OSC-REF1 I/O
ANALOG
AVDD0/AGND0
Reference resistor for VCO1 is connected
17
OSC-LIM1 I/O
ANALOG
AVDD0/AGND0
Control current resistor is connected (for VCO1)
18
PC1-FIL
I/O
ANALOG
AVDD0/AGND0
External filter for PC1
19
AGND0
-
-
Analog system GND
(GND in PLL system)
20
DGND0
-
-
digital system GND
(GND in PLL system)
21
HDOUT
O
CMOS
DVDD0/DGND0
H-OUT is outputted
22
DVDD0
-
-
digital system power supply
(power supply in PLL system)
23
FBP-IN
I
TTL
5V withstand
DVDD0/DGND0
Horizontal fly-back pulse is inputted
Schmidt
24
TEST2
O
CMOS
DVDD0/DGND0
For LSI test
25
H-OUT2
O
CMOS
DVDD0/DGND0
H-OUT outputted at fH and 1/2fH periods
26
POC-IN
I
ANALOG
DVDD0/DGND0
Sense voltage of Power On Clear is inputted
27
POC-OUT
O
Nch Open
5V withstand
DVDD0/DGND0
Signal of Power On Clear is outputted
Drain
28-30
P0-P2
O
CMOS
DVDD1/DGND1
Universal port output
31
DVDD1
-
-
digital system power supply
(VDD in logic system)
32-34
P3
O
CMOS
DVDD1/DGND1
Universal port output
33
VSH
O
CMOS
DVDD1/DGND1
Pulse for DV SHAPE is outputted
Pulse of width 50us from V-IN leading edge
34 VSAWRST
O
CMOS
DVDD1/DGND1
Pulse for DV SHAPE is outputted
Pulse of width 150us from V-IN leading edge
35
BLK
O
CMOS
DVDD1/DGND1
Blanking is outputted
CR1 chassis (E)
12
No
Pin name
I/O
Level
PU/PD [kW]
Power supply
Functional description
for buffer
36
V-IN
I
TTL
5V withstand
DVDD1/DGND1
V sync signal is inputted
Schmidt
37
DGND1
-
-
digital system GND
(GND in logic system)
38
H-IN
I
TTL
5V withstand
DVDD1/DGND1
H sync signal is inputted
Schmidt
39 LOCK-DET
O
Nch Open
5V withstand
DVDD1/DGND1
Horizontal Lock detection is outputted
Drain
40
SDA
I/O
Nch Open
5V withstand
DVDD1/DGND1
Serial data of IIC bus is inputted and outputted
Drain
Schmidt
41
SCL
I
TTL
5V withstand
DVDD1/DGND1
Serial clock of IIC bus is inputted
Schmidt
42
RESET
I
TTL
5V withstand
DVDD1/DGND1
Reset is inputted
43-46 PWM0-3
O
CMOS
DVDD1/DGND1
PWM outputted
PWM 0, 1 : 9 bit PWM 2, 3 : 8 bit
47
DVDD2
-
-
-
digital system power supply
(VDD in 1 bit DAC system)
48
GYSC
O
ANALOG
DVDD2/DGND2
Y line static convergence waveform for Green
(1 bit D/A)
49
GXSC
O
ANALOG
DVDD2/DGND2
X line static convergence waveform for Green
(1 bit D/A)
50
VDF
O
ANALOG
DVDD2/DGND2
Vertical dynamic focus waveform is outputted
(1 bit D/A)
51
VKEY
O
ANALOG
DVDD2/DGND2
NS distortion-corrected waveform is outputted
(1 bit D/A)
52
YSC
O
ANALOG
DVDD2/DGND2
Y line static convergence waveform
(1 bit D/A)
53
XSC
O
ANALOG
DVDD2/DGND2
X line static convergence waveform
(1 bit D/A)
54
HSHAPE
O
ANALOG
DVDD2/DGND2
Corrected waveform in horizontal size system is
outputted
(1 bit D/A)
55
DGND2
-
-
digital system GND
(GND in 1 bit DAC system)
56
TEST3
I
CMOS
DVDD2/DGND2
For LSI test
57
TEST4
I
CMOS
DVDD2/DGND2
For LSI test
58
ASW1
O
CMOS
AVDD1/AGND1
Analog SW for V-SAW
59
ASW2
O
CMOS
AVDD1/AGND1
Analog SW for V-SAW
60
AGND1
-
-
Analog system GND
(GND in DAC system)
61
VSAWL
O
ANALOG
AVDD1/AGND1
V-SAW lower side is outputted
62
VSAWH
O
ANALOG
AVDD1/AGND1
V-SAW upper side is outputted
63
YDC
O
ANALOG
AVDD1/AGND1
Y line dynamic convergence waveform
(R-strings DAC)
64
DCC
O
ANALOG
AVDD1/AGND1
Center voltage of 10 bit R-String DAC is
outputted
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