Sony DVP-S7000 (serv.man2) Service Manual ▷ View online
– 130 –
6-3-2.
External View
1
2
3 4
5
6
7
8
9 10
16
15
14
13
12
11
20
19
18
17
21 22 23 24 25 26 27 28 29 30
33
34
35
36
37
38
39
40
41
42
43
44
45
46
48
47
31
32
50
49
56 55 54 53 52 51
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
80
73
74
75
76
77
78
79
81
82
92
91
90
89
88
87
86
85
84
83
93
94
95
96
97
98
99
100
CXD2545Q
XRST
DIRC
SCLK
DFSW
ATSK
DATA
XLAT
CLOK
COUT
V
DD
MIRR
DFCT
FOK
FSW
MON
MDP
MDS
LOCK
SSTP
SFDR
SRON
SRDR
SFON
TFDR
TRON
TRDR
TFON
FFDR
FRON
FRDR
FFON
VCOO
VCOI
TEST
Vss
TES2
TES3
PDO
VPCO
VCKI
AV
DD
IGEN
AVss
ADIO
RFC
RFDC
TE
SE
FE
VC
FILO
FILI
PCO
CLTV
AVss
RFAC
BIAS
ASYI
ASYO
AV
DD
V
DD
ASYE
PSSL
WDCK
LRCK
DA16
DA15
DA14
DA13
DA12
DA11
DA10
DA09
DA08
DA07
DA06
DA05
DA04
DA03
DA02
DA01
XTAI
XTAO
XTSL
Vss
FSTI
FSTO
FSOF
C16M
MD2
DOUT
EMPH
WFCK
SCOR
SBSO
EXCK
SQSO
SQCK
MUTE
SENS
Figure 6-6.
External view
6-3-3.
Pin Assignment
Pin No.
Signal Name
I/O
Functional Description
1
SRON
O
2
SRDR
O
Output of sled drive
3
SFON
O
4
TFDR
O
5
TRON
O
Output of tracking drive
6
TRDR
O
7
TFON
O
8
FFDR
O
9
FRON
O
Output of focus drive
10
FRDR
O
11
FFON
O
12
VCOO
O
Output of oscillation circuit for analog EFM PLL
13
VCOI
I
Input of oscillation circuit for analog EFM PLL
f
LOCK
=8.6436MHz
14
TEST
I
Test pin. Normally ground
15
V
SS
—
Digital ground
16
TES2
I
Test pin. Normally ground
17
TES3
I
18
PDO
O
Output of charge pump for analog EFM PLL
19
VPCO
O
Output of PLL charge pump for variable pitch
– 131 –
Pin No.
Signal Name
I/O
Functional Description
20
VCKI
I
Input of clock from external VCO for variable pitch
fcenter=16.9344MHz
21
AV
DD
—
Analog power supply
22
IGEN
I
Connect OPE AMP current source reference resistor for
digital servo
23
AV
SS
—
Analog ground
24
ADIO
O
A/D converter input monitor pin
25
RFC
I
Connect low pass filter capacitor for RFDC input
26
RFDC
I
Input of RF signal
Input range 2.15 to 5.0V (at VDD=AVDD=5.0V)
27
TE
I
Input of tracking error signal
Input range 2.5±1.0V (at VDD=AVDD=5.0V)
28
SE
I
Input of sled error signal
Input range 2.5±1.0V (at VDD=AVDD=5.0V)
29
FE
I
Input of focus error signal
Input range 2.5±1.0V (at VDD=AVDD=5.0V)
30
VC
I
Input of center voltage
31
FILO
O
Output of filter for master PLL
32
FILI
I
Input of filter for master PLL
33
PCO
O
Output of charge pump for master PLL
34
CLTV
I
Input of VCO control voltage for master
35
AV
SS
—
Analog ground
36
RFAC
I
Input of EFM signal
37
BIAS
I
Input of asymmetry circuit constant current
38
ASYI
I
Input of asymmetry comparator voltage
39
ASYO
O
EFM full swing output (L=VSS, H=VDD)
40
AV
DD
—
Analog power supply
41
V
DD
—
Digital power supply
42
ASYE
I
Asymmetry circuit ON/OFF (L=OFF, H=ON)
43
PSSL
I
Audio data output mode selection (L=Serial, H=Parallel)
44
WDCK
O
D/A interface for 48-bit slots. Word clock f=2FS
45
LRCK
O
D/A interface for 48-bit slots. LR clock f=FS
46
DA16
O
DA16 output when PSSL=1, or 48-bit slot serial data output
when PSSL=0
47
DA15
O
DA15 output when PSSL=1, or 48-bit slot bit clock output
when PSSL=0
48
DA14
O
DA14 output when PSSL=1, or 64-bit slot serial data output
when PSSL=0
49
DA13
O
DA13 output when PSSL=1, or 64-bit slot bit clock output
when PSSL=0
50
DA12
O
DA12 output when PSSL=1, or 64-bit slot LR clock output
when PSSL=0
– 132 –
Pin No.
Signal Name
I/O
Functional Description
51
DA11
O
DA11 output when PSSL=1, or GTOP output when PSSL=0
52
DA10
O
DA10 output when PSSL=1, or XUGF output when PSSL=0
53
DA09
O
DA09 output when PSSL=1, or XPLCK output when PSSL=0
54
DA08
O
DA08 output when PSSL=1, or GFS output when PSSL=0
55
DA07
O
DA07 output when PSSL=1, or RFCK output when PSSL=0
56
DA06
O
DA06 output when PSSL=1, or C2PO output when PSSL=0
57
DA05
O
DA05 output when PSSL=1, or XRAOF output when PSSL=0
58
DA04
O
DA04 output when PSSL=1, or MNT3 output when PSSL=0
59
DA03
O
DA03 output when PSSL=1, or MNT2 output when PSSL=0
60
DA02
O
DA02 output when PSSL=1, or MNT1 output when PSSL=0
61
DA01
O
DA01 output when PSSL=1, or MNT0 output when PSSL=0
62
XTAI
I
Input of crystal oscillation circuit 16.9344MHz or 33.8688MHz
63
XTAO
O
Output of crystal oscillation circuit
64
XTSL
I
Input of crystal oscillation circuit. “L” when crystal is
16.9344MHz, or “H” when 33.8688MHz (at normal play).
65
V
SS
—
Digital ground
66
FSTI
I
Input of reference clock for digital servo block
67
FSTO
O
Output of 2/3 frequency of 62 & 63 pins. It does not change
by variable pitch.
68
FSOF
O
Output of 1/4 frequency of 62 & 63 pins. It does not change
by variable pitch.
69
C16M
O
Output of 16.9344MHz. It changes by variable pitch
(at normal play).
70
MD2
I
Digital-out ON/OFF control (L=OFF, H=ON)
71
DOUT
O
Digital-out output
72
EMPH
O
Output of emphasis mode of playing disc
(L: Without emphasis, H: With emphasis)
73
WFCK
O
Output of WFCK
74
SCOR
O
Output of subcode sync
(H when either subcode sync S0 or S1 is detected)
75
SBSO
O
Sub P-W serial output
76
EXCK
I
Input of clock for reading out SBSO
77
SQSO
O
SubQ 80 bits and PCM peak level data 16 bits output
78
SQCK
I
Input of clock for reading out SQSO
79
MUTE
I
Mute selection (Mute at H)
80
SENS
O
Output of SENS to CPU
81
XRST
I
System reset (Reset at L)
82
DIRC
I
Used at one track jump
(VDD level is entered, if not used)
83
SCLK
I
Input of clock for reading out SENS serial data
84
DFSW
I
DFCT switching pin (DFCT preventive circuit OFF at H)
85
ATSK
I
Pin for anti-shock
– 133 –
Pin No.
Signal Name
I/O
Functional Description
86
DATA
I
Serial data input from CPU
87
XLAT
I
Latch input from CPU
88
CLOK
I
Input of serial data transfer clock from CPU
89
COUT
O
Output of track count signal
90
V
DD
—
Digital power supply
91
MIRR
O
Output of mirror signal
92
DFCT
O
Output of defect signal
93
FOK
O
Output of focus OK signal
94
FSW
O
Output of spindle motor output filter select signal
95
MON
O
Output of spindle motor ON-OFF control signal
96
MDP
O
Output of spindle motor servo control signal
97
MDS
O
Output of spindle motor servo control signal
98
LOCK
O
GFS is sampled at 460Hz and “H” is output when GFS is “H”,
or “L” is output when GFS is “L” 8 times continuously.
99
SSTP
I
Input of disc most-inside track detection signal
100
SFDR
O
Sled drive output
Notes: • For 64-bit slots, 2’s complementary signal, LSB first, is output. For 48-bit slots, 2’s
complementary signal, MSB first, is output.
• GTOP monitors protection status of frame sync signal. (H: Sync protection window open)
• XUGF is a frame sync signal obtained from EFM signal, and it is a negative pulse which is a
signal before sync protection.
• XPLCK is inverted clock of EFM PLL. PLL is generated so that a falling edge meets with a
transition point of EFM signal.
• GFS signal becomes “H” when frame sync coincides with the insertion protection timing.
• RFCK is a signal of 136µs period generated at crystal accuracy.
• C2PO indicates data error status.
• XRAOF is generated when 32K RAM exceeds ±28 frame jitter margin.
