Sony DVP-S7000 (serv.man2) Service Manual ▷ View online
– 126 –
6-2-2.
Pin Assignment
Pin No.
Signal Name
I/O
Functional Description
1
VDD
—
Digital positive power supply
2
CKTS2
I
Test pin in VCOCK system (normally fixed to “L”)
3
VDD
—
Digital positive power supply
4
VSS
—
Digital ground
5
CKTS
I
Test pin in VCOCK system (normally fixed to “L”)
6
XPNM
O
PLL mode output (NORMAL mode at “L”)
7
XPCP
O
PLL mode output (CAPTURE mode at “L”)
8
XPFX
O
PLL mode output (FIX mode at “L”)
9
GRL
O
Signals for CLV
10
GRU
O
11
NRZI
O
Output of binary-valued RF wave
(sampling at double accuracy, for CLV)
12
RFD
O
Output of binary-valued RF wave (sampling with channel clock)
13
PLCK
O
Output of channel clock
14
XPLCK
O
Output of channel clock (inverted)
15
VSS
—
Digital ground
16
TEST
I
Test pin (normally fixed to “L”)
17
GFS
I
Input of PLL sequence select signal
18
RGFS
I
19
FCLK
I
Input of frame frequency
20
CK17M
I/O
Input/output of external clock 16.9344MHz
21
RFMN11
O
22
RFMN10
O
23
RFMN9
O
24
RFMN8
O
RF monitor output. Complement of 2 of 12 bits.
25
RFMN7
O
26
RFMN6
O
27
RFMN5
O
28
VDD
—
Digital positive power supply
29
VSS
—
Digital ground
30
RFMN4
O
31
RFMN3
O
32
RFMN2
O
RF monitor output. Complement of 2 of 12 bits.
33
RFMN1
O
34
RFMN0
O
35
DRF7
I/O
36
DRF6
I/O
37
DRF5
I/O
Input/output of RF sample value. 8-bit offset binary.
38
DRF4
I/O
39
DRF3
I/O
40
VSS
—
Digital ground
– 127 –
Pin No.
Signal Name
I/O
Functional Description
41
DRF2
I/O
42
DRF1
I/O
Input/output of RF sample value. 8-bit offset binary.
43
DRF0
I/O
44
VSS
—
Digital ground
45
VSS
—
Analog ground
46
AIN
I
RF analog input (AD converter input)
47
VRH
I
ADC reference voltage (H)
48
VRM
O
ADC reference voltage (Center, for decoupling)
49
VRL
I
ADC reference voltage (L)
50
VDD
—
Analog positive power supply
51
VDD
—
Digital positive power supply
52
AGC
O
Output of AGC gain control signal (ternary-valued PWM)
53
VDD
—
Digital positive power supply
54
VSS
—
Digital ground
55
ADPD
I
ADC power down (fixed to “L” when using built-in ADC)
56
ADTS
I
ADC test pin (normally fixed to “L”)
57
XRST
I
Reset
58
CPDI
I
Input of serial data
59
CPCK
I
Input of serial data sync clock
60
XLT
I
Input of serial data latch
61
ENV
O
Output of envelope detect signal (normally fixed to “H”)
62
LMTO
O
Output of clock limiter status
63
LMTI
I
Input of clock limit
64
EXFC
I
Input of frame frequency input/output select signal.
Input mode at “H”
65
VSS
—
Digital ground
66
NSO
O
Output of no-signal status signal. “H” when no signal is
present at AIN input.
67
NSI
I
PLL mode is forcibly fixed at “H”
68
LPON
I
Normally fixed to “H”. At “L”, input data to built-in D/A
converter becomes “7F”.
69
PLOK
O
Output of PLL sync. “H” when PLL is locked normally.
70
CPDO
O
Output of serial data
71
SOINT
O
Serial data request. “L” active
72
SOEN
I
Serial data enable. “L” active
73
DACK
I
Input of clock for DAC
74
POCK
O
Output of clock for DAC (connected directly to DACK)
75
MNO7
O
76
MNO6
O
PLL monitor output
77
MNO5
O
78
VDD
—
Digital positive power supply
79
VSS
—
Digital ground
– 128 –
Pin No.
Signal Name
I/O
Functional Description
80
MNO4
O
81
MNO3
O
82
MNO2
O
PLL monitor output
83
MNO1
O
84
MNO0
O
85
DATS
I
DAC test pin (normally fixed to “L”)
86
DAPD
I
DAC power down (fixed to “L” when using built-in DAC)
87
VCOCK
I
Input of VCO clock. Connected directly to OVCO, or input
from external VCO
88
OVCO
O
Output of VCO oscillation wave
89
VCNG
O
Output of VCO control voltage offset selection
90
VSS
—
Digital ground
91
VSS
—
Analog ground
92
AVCO
I
Input of VCO control voltage
93
VDD
—
Analog positive power supply
94
VSS
—
Analog ground
95
VREF
I
Input of DAC reference voltage
96
VDD
—
Analog positive power supply
97
RFS
O
Output of DAC reference current
(connect CR otherwise specified)
98
VDD
—
Analog positive power supply
99
AOUT
O
Output of VCO control voltage (DAC output)
100
VSS
—
Analog ground
* DRF7 to DRF0 are output pins only in the A/D test mode (ADTS=High).
– 129 –
6-3. Digital Signal Processor
CXD2545Q (IC717 on MB-75 board)
6-3-1.
Block Diagram
Figure 6-5.
Block diagram
68
69
CLOCK
GENERATOR
13
18
32
33
31
34
36
38
39
42
73
74
75
76
72
78
77
95
94
96
97
12
DIGITAL PLL
VARI-PITCH
DOUBLE SPEED
(
(
EFM
DEMODULATOR
SYNC
PROTECTOR
ASYMMETRY
CORRECTION
CORRECTION
MUX
TIMING
GENERATOR 1
SUBCODE
P-W
PROCESSOR
SUBCODE
Q
PROCESSOR
CLV
PROCESSOR
18-TIMES
OVERSAMPLING
FILTER
NOISE
SHAPER
REGISTER
32K RAM
ERROR CORRECTOR
TIMING
GENERATOR 2
SERVO
INTERFACE
SERVO
AUTO
SEQUENCER
DIGITAL OUT
PEAK DETECTOR
ADDRESS
GENERATOR
PRIORITY
ENCODER
ENCODER
D/A
DATA PROCESSOR
SERIAL/PARALLEL
PROCESSOR
MIRR
DFCT
FOK
SERVO DSP
PWM GENERATOR
FOCUS PWM
GENERATOR
TRACKING PWM
GENERATOR
SLED PWM
GENERATOR
26
27
28
29
30
62
67
63 64
20 19
TRACKING SERVO
FOCUS SERVO
SLED SERVO
16
SWITCH
&
BUFFER
A/D
CONVERTER
43
79
70
71
88
87
86
CPU INTERFACE
80
89
92
91
93
2
2
2
2
2
2
24
25
17
16
14
21
23 35
40
41 90 15 65
81
SIGNAL PROCESSING BLOCK
SERVO BLOCK
FSTO
XTAI
XTAO
XTSL
VCKI
VPCO
FSOF
C16M
PDO
VCOI
VCOO
PCO
FILI
FILO
CLTV
RFAC
ASYI
ASYO
ASYE
WFCK
SCOR
EXCK
SBSO
EMPH
SQCK
SQSO
MON
FSW
MDP
MDS
RFDC
TE
SE
FE
VC
RFC
ADIO
TEST
TES2
TES3
AV
DD
AV
DD
V
DD
V
DD
Vss
Vss
AVss
AVss
XRST
CLTV
MUTE
DOUT
MD2
DATA
CLOK
XLAT
SENS
COUT
MIRR
DFCT
FOK
SFDR, SFON
SRDR, SRON
TFDR, TFON
TRDR, TRON
FFDR, FFON
FRDR, FRON
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