Sony DVP-S7000 (serv.man2) Service Manual ▷ View online
– 122 –
Figure 6-2.
Block diagram
6-1-2.
External View
Figure 6-3.
External view
1
2
3
4
5
6
7
8
9
10
16
15
14
13
12
11
33
34
35
36
37
38
39
40
41
42
43
44
45
46
48
47
56 55 54 53 52 51 50 49
57
58
59
60
61
62
63
64
20
19
18
17
21 22 23 24 25 26 27 28 29 30 31 32
A2
B2
C2
C2
D2
CP
CN
D
C
B
A
B
A
VNB
E
F
F
G
H
LDON
LOW Z
HOLD1
HOLD1
IDSEL
SDEN
SDATA
SCLK
HOLD2
BYP2
PP
FE
TE
PI
MIN
MLPF1
MLPF2
FDCHG
RFN
RFP
ATOP
ATON
AIN
AIP
VPA
SIGO
BYP
RX
DIN
DIP
FNP
FNN
VNA
PWRON
SSI33P3720
PD
LD
TI OF
TI-A
TI-B
TISUM
TII
TI-
TIO
TIE
VC
VCI
VPB
MIRR
MP
MB
APC
12/3
dB
PEAK/
BTTOM
HOLD
+
–
–
SERIAL
PORT
REGISTER
OFFSET
FROM
S-PORT
HYS SEL
FROM
S-PORT
+
+
+
22
23
24
25
+
–
GCA
17
27
28
20
19
21
11
29
50
58
26
43
44
45
30
18
16
34
35
36
31
32
33
LPSEL
FROM
S-PORT
Gain Sel FROM
S-PORT
VC for
internal
3
FROM
S-PORT
VC
+
–
–
FROM
S-PORT
LDL/H
PD
VCI
VC
TI OF
TI-A
TI-B
TISUM
TII
TI-
TIO
VNB
VNA
VPB
VPA
TIE
SCLK
SDATA
SDEN
MIRR
FDCHG
MB
MP
MLPF2
MLPF1
MIN
LD
LDON
TILT
Error
INPUT
Error
INPUT
MIRROR
– 123 –
6-1-3.
Pin Assignment
Pin No.
Signal Name
I/O
Functional Description
1
A2
I
2
B2
I
Input of photo detection signals
3
C2
I
4
D2
I
5
CP
—
Differential phase tracking LPF pins
6
CN
—
7
D
I
8
C
I
Input of photo detection signals
9
B
I
10
A
I
11
VNB
—
Ground for servo block
12
E
I
13
F
I
Input of sub beam photo detection signals
14
G
I
15
H
I
16
LDON
I
APC output ON/OFF
17
PD
I
APC input
18
LD
O
APC output
19
TIOF
I
Tilt sensor offset
20
TI-A
I
Input of tilt sensor A
21
TI-B
I
Input of tilt sensor B
22
TISUM
O
Summing output of TI-A and TI-B
23
TII
O
Sub tracking output of TI-A and TI-B
24
TI-
—
Phase compensation filter pins
25
TIO
—
26
TIE
O
Output of tilt error signal
27
VC
—
Output of reference voltage
28
VCI
—
Input of reference voltage
29
VPB
—
Power supply for servo block
30
MIRR
O
Output of mirror detection
31
MP
—
Mirror signal peak hold
32
MB
—
Mirror signal bottom hold
33
FDCHG
I
Low impedance enable
34
MLPF2
—
Mirror signal LPF pins
35
MLPF1
—
36
MIN
I
Input of RF signal for mirror
37
PI
O
Output of pull-in signal
38
TE
O
Output of tracking error signal
39
FE
O
Output of focus error signal
40
PP
O
Output of push-pull monitor
– 124 –
Pin No.
Signal Name
I/O
Functional Description
41
BYP2
—
Connect servo AGC integral capacitor CBYP2 between
BYP2 and VPB
42
HOLD2
I
Hold control
43
SCLK
I
Serial clock
44
SDATA
I/O
Serial data
45
SDEN
I
Serial data enable
46
IDSEL
I
ID/user data gate
47
HOLD1
I
Hold control
48
LOWZ
I
Low impedance enable
49
PWRON
I
Power enable
50
VNA
—
Ground for RF block, serial port
51
FNN
O
Differential normal output
52
FNP
O
53
DIP
I
Analog input for RF signal buffer
54
DIN
I
55
RX
—
Reference resistance
56
BYP
—
Connect RF AGC integral capacitor CBYP between BYP
and VPA
57
SIGO
O
Single end normal output
58
VPA
—
Ground for RF block, serial port
59
AIP
I
Input of AGC amplifier
60
AIN
I
61
ATON
O
Output of differential attenuator
62
ATOP
O
63
RFP
I
Input of RF signal
64
RFN
I
– 125 –
6-2. RF Processor
CXD8599Q (IC770 on MB-75 board)
6-2-1.
Block Diagram
Figure 6-4.
Block diagram
DIVIDER
FCLK
RUNDET
CKLMT
PLL
VCO
DAC
CLV
P/S
JIT
RNG
AAC
EQ
AGC
ADC
RFDET
I/F
RF[7..0]
LF0[7..0]
FCLK
CK17M
EXFC
AIN
VRH
VRM
VRL
ADPD
DRF[7..0]
AGC
ENV
NSO
NSI
RFMN[11..0]
CPDI
CPCK
XLT
GFS
RGFS
XPFX
XPCP
XPNM
XRST
TEST
CKTS,CKTS2
ADTS
DATS
AVCO
OVCO
RFD
LMTO
LMTI
VCOCK
VCNG
PLCK
XPLCK
LPON
AOUT
RFS
VREF
DAPD
DACK
MNO[7..0]
POCK
PLOK
NRZI
GRL
GRU
SOEN
SOINT
CPDO
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