Sony DVP-NS3100ES Service Manual ▷ View online
21
DVP-NS3100ES
A
1.0
±
0.05 Vp-p
6-2-3.
Checking S Video Output S-Y
<Purpose>
Check S-terminal video output. If it is incorrect, pictures will not
be displayed correctly in spite of connection to the monitor with a
S-terminal cable.
Check S-terminal video output. If it is incorrect, pictures will not
be displayed correctly in spite of connection to the monitor with a
S-terminal cable.
Mode
Video level adjustment in test mode
Signal
Color bars
Check point
S VIDEO OUT (S-Y) connector (J501)
(75
Ω
terminated)
Instrument
Oscilloscope
Specification
1.0
±
0.05 Vp-p
Checking method:
1) In the Test Mode Menu, select the “6. Video Level Adjustment”
so that color bars are generated.
2) Confirm that the S-Y level is 1.0
±
0.05 Vp-p.
Fig. 6-3
6-2-4.
Checking S Video Output S-C
<Purpose>
This checks whether the S-C satisfies the NTSC standard. If it is
not correct, the colors will be to dark or light.
This checks whether the S-C satisfies the NTSC standard. If it is
not correct, the colors will be to dark or light.
Mode
Video level adjustment in test mode
Signal
Color bars
Check point
S VIDEO OUT (S-C) connector (J501)
(75
Ω
terminated)
Instrument
Oscilloscope
Specification
A = 286
±
30 mVp-p
Checking method:
1) In the Test Mode Menu, select the “6. Video Level Adjustment”
so that color bars are generated.
2) Confirm that the S-C burst is “A”.
Fig. 6-4
1.0
±
0.05 Vp-p
6-2-5.
Checking Component Video Output Y
<Purpose>
This checks component video output Y. If it is incorrect, correct
brightness will not be attained when connected to, for instance,
projector.
This checks component video output Y. If it is incorrect, correct
brightness will not be attained when connected to, for instance,
projector.
Mode
Video level adjustment in test mode
Signal
Color bars
Check point
COMPONENT VIDEO OUT (Y)
connector (J620) (75
Ω
terminated)
Instrument
Oscilloscope
Specification
1.0
±
0.05 Vp-p
Checking method:
1) In the Test Mode Menu, select the “6. Video Level Adjustment”
so that color bars are generated.
2) Confirm that the Y level is 1.0
±
0.05 Vp-p.
Fig. 6-5
6-2-6.
Checking Component Video Output B-Y
<Purpose>
This checks component video output B-Y. If it is incorrect, correct
colors will not be displayed when connected to, for instance,
projector.
This checks component video output B-Y. If it is incorrect, correct
colors will not be displayed when connected to, for instance,
projector.
Mode
Video level adjustment in test mode
Signal
Color bars
Check point
COMPONENT VIDEO OUT (P
B
/C
B
)
connector (J660) (75
Ω
terminated)
Instrument
Oscilloscope
Specification
700
±
50 mVp-p
Checking method:
1) In the Test Mode Menu, select the “6. Video Level Adjustment”
so that color bars are generated.
2) Confirm that the B-Y level is 700
±
50 mVp-p.
Fig. 6-6
700
±
50 mVp-p
22
DVP-NS3100ES
Adjustment Location:
RV601
Video Level Adjustment
RV600
Progressive Video
Output Level Adjustment
– MAIN Board (Side A) –
700
±
50 mVp-p
6-2-7.
Checking Component Video Output R-Y
<Purpose>
This checks component video output R-Y. If it is incorrect, correct
colors will not be displayed when connected to, for instance,
projector.
This checks component video output R-Y. If it is incorrect, correct
colors will not be displayed when connected to, for instance,
projector.
Mode
Video level adjustment in test mode
Signal
Color bars
Check point
COMPONENT VIDEO OUT (P
R
/C
R
)
connector (J102) (75
Ω
terminated)
Instrument
Oscilloscope
Specification
700
±
50 mVp-p
Checking method:
1) In the Test Mode Menu, select the “6. Video Level Adjustment”
so that color bars are generated.
2) Confirm that the R-Y level is 700
±
50 mVp-p.
Fig. 6-7
DVP-NS3100ES
23
23
DVP-NS3100ES
SECTION 7
DIAGRAMS
7-1. BLOCK DIAGRAM – SERVO SECTION –
PARALELL DATA BUS
ADDRESS BUS
PARALELL DATA BUS
ADDRESS BUS
A
CPU
IC256
DVD INTERFACE
IC105
OPTICAL
TRAVERSE UNIT
(DBU-3)
FOCUS/TRACKING COIL DRIVE,
SLED/SPINDLE/LOADING MOTOR DRIVE
IC103
FACT
A
6
RFOUT
BE_SDA
27M_FE
BE_SCL
VREF (+2.7V)
FREIN
CPU-DA
TA
(0) –
CPU-DA
TA
(15)
ADDR1 – ADDR7
DATA0 – DATA15
DQ0 – DQ14, DQ15A-1
A0 – A20
FLASH MEMORY
IC253
YC0 – YC7
YC0 – YC7
A0 – A11,
BA0, BA1
SMI-DATA (0) –
SMI-DATA (15)
DQ0 – DQ15
SD-RAM
IC254
SMI-CLKOUT
CLK
RFSACD
7
DIGITAL VIDEO
8
PCM
9
HDMI_CLK
10
DAC_CLK
11
ADY_CS
13
SACD, I2S
14
BE_RST
16
I2C
2
LDM
1
CPU-I/F
3
SYS CLK
4
YC_CLKOUT
H_INT_B
VIDEO_RST
B
B
8
RFIN
3
B-DATA
16
4
OUT-DATA 64
RFSACD 99
B-BCLK
17
OUT-CLK 61
YC_CLKOUT 3
IRQ (1) 126
VIDEO_RST 9
PCM_DATA0
PCM_DATA3
SPDIF
PCM_SCLK
PCM_LRCK
SI
SO
SCLK
DAC-PCMOUT3 2
SPDIF-OUT 57
DAC-SCLK 51
DAC-LRCK 56
SI 206
SO 207
SCLK 208
RCLK 105
PCM_DATA1
PCM_DATA2
DAC-PCMOUT0 52
DAC-PCMOUT1 53
DAC-PCMOUT2 54
B-FLAG
18
OUT-DVALID 63
WCLK
20
OUT-EVALID 59
RSERROR
187
OUT-ERR 58
B-SYNC
19
OUT-SYNC 65
B-V4
21
SER
14
SRCLK
11
IRQ (0)
127
IRQ_FE 71
FE_RST
186
RESET-N 81
BE_SDA
194
SDA 67
BE_SCL
195
SCL 66
C
C
14
D
D
12
E
E
21
F
F
20
DVD LD
LD1
89
PD
LMD1
93
LMD2
94
AUTOMATIC
POWER CONTROL
(FOR DVD)
Q101, 102
CD LD
LD2
90
SW
DVD/CD
43
INLIM
INLIM
45
VC
FCS+
REFD
10
36
1
33
TACT
34
DISC
28
SLED
29
SP
44
SPDIR
70
MUTE_SP
36
MUTE_DRV
37
4
7
10
13
15
REF
32
87
17
21
20
19
38
15
16
FCS+
37
TRK+
35
TRK–
34
SLEDA+
32
SLEDA–
31
SLEDB+
30
SLEDB–
29
SPDL+
27
SPDL–
28
41
42
25
24
AUTOMATIC
POWER CONTROL
(FOR CD)
Q103, 104
M151
(LOADING)
M
3.3V-D
LOW-PASS FILTER
IC102 (1/3)
CENTER VOLTAGE
GENERATOR
IC102 (3/3)
REFERENCE VOLTAGE
GENERATOR
IC102 (2/3)
RF FILTER
Q105
39 – 46
SA_CS
SACD BUS
15
SA_RW
I2S_DATA_OUT
I2S_BCLK_OUT
I2S_BFLAG_OUT
I2S_WCK_OUT
I2S_SYNC_OUT
FUR_RST
CPU-RW 130
I2S_DATA_OUT 6
I2S_BCLK_OUT 7
I2S_BFLAG_OUT 8
I2S_WCK_OUT 196
I2S_SYNC_OUT 193
FUR_RST 1
DATA0 – DATA15
ADDR1 – ADDR21
DATA0 – DATA15
ADDR1 – ADDR7
SA_IRQ
SA_WAIT
CPU-CE (2) 133
IRQ (2) 125
CPU-WAIT 131
RCLK
12
XRCLR 22
QD 3
QE 4
QC 2
QB 1
QA 15
RCLR
13
BUFFER
IC556
INVERTER
IC258
HDMI_LRCK
HDMI_SCLK
DAC_LRCK
DAC_SCLK
CSWO_CS
DLDRO_CS
SLSRO_CS
FLFRO_CS
SCLK
SO
AUDIO
12
SHIFT REGISTER
IC257
BE_RXD
BE_BUSY
TMODE_SW
27M_BE
BE_BUSY
11
TMODE_SW
103
BE_TXD
BE_CS
IF_TXD
197
PIX-CLK
120
IF_RXD
200
SQUEEZE
5
BE_A_MUTE
6
BE_A_MUTE
188
SQUEEZE
191
512FS_BE
DAC-PCMCLK
55
BE_CS
13
84 – 93,
97 – 102
141 – 148,
151 – 158
CPU-ADR (1) –
CPU-ADR (21)
161 – 170,
173 – 183
SMI-ADR (0) –
SMI-ADR (13)
2, 4, 5, 7, 8, 10,
11, 13, 42, 44, 45,
47, 48, 50, 51, 53
69 – 66,
58 – 63,
58 – 63,
70 – 73
23 – 26,
29 – 34,
29 – 34,
22, 35
95
SMI-CLKIN
82
38
SMI-CS (0)
CS
74
19
SMI-RAS
RAS
76
18
SMI-CAS
CAS
77
17
SMI-WE
WE
78
16
SMI-DQML
LDQM
79
15
SMI-DQMU
UDQM
80
39
CPU-BE (0)
W
128
11
RP
12
CPU-OE
G
117
28
CPU-CE (3)
E
132
26
LDM+
LDM–
29, 31, 33, 35, 38, 40, 42, 44,
30, 32, 34, 36, 39, 41, 43, 45
25 – 18, 8 –1,
17, 16, 9, 10
DQ0 – DQ14, DQ15A-1
FLASH MEMORY
IC255
W
11
RP
12
G
28
CPU-CE (1)
E
134
RESET
124
26
29, 31, 33, 35, 38, 40, 42, 44,
30, 32, 34, 36, 39, 41, 43, 45
25 – 18, 8 –1,
17, 16, 9, 10
DATA0– DATA15
DATA0– DATA15
ADDR1 – ADDR21
ADDR1 – ADDR21
: PLAY (AUDIO)
: PLAY (VIDEO)
SIGNAL PATH
A0 – A20
(Page 27)
(Page 26)
(Page 24)
(Page 24)
(Page 26)
(Page 25)
(Page 24)
(Page 24)
(Page 24)
(Page 24)
(Page 24)
(Page 24)
(Page 24)
(Page 25)
(Page 26)
(Page 26)
DVP-NS3100ES
24
24
DVP-NS3100ES
7-2. BLOCK DIAGRAM – AUDIO SECTION (1/2) –
PCM_DATA0
PCM_DATA3
SPDIF
PCM_SCLK
PCM_LRCK
SI
SO
SCLK
DLDRI
63
SPDIFI
57
BCKI
60
LRLKI
59
SO
75
SI
PCM
9
DAC_CLK
11
ADY_CS
13
74
DAC_SCLK
DAC_LRCK
SCLK
72
XCS
73
CLK512
68
XRST
70
PCM_DATA1
PCM_DATA2
FLFRI
66
SLSRI
65
CSWI
64
HDMI_FLFRO
HDMI_SPDIF
DLDRO 44
SPDIFO 49
FLFRO 47
SLSRO 46
CSWO 45
LIP SYNC ADJUST
IC552
SACD MEDIA PLAYER
IC502
HDMI_SLSRO
HDMI_CSWO
HDMI_DLDRO
BUFFER
IC554
DSD_PCM_5 114
DSD_PCM_9 120
DSD_PCM_11 121
DSD_PCM_6 115
DSD_PCM_1 109
DSD_PCM_2 110
DSD_PCM_3 111
DSD_PCM_4 113
DSD_PCM_0 108
BUFFER
IC504
D0 – D15
DQ0 – DQ15
A0 – A11
15 WE
10
WE
16 CAS
11
CAS
17 RAS
12
RAS
18 CS
13
CS
34 CKE
15
CKE
35 CLK
14
CLK
A0 – A9, A10/AP
A11 (BA)
SD-RAM
IC555
100, 1 – 5, 7, 8,
98, 97, 95 – 90
D_DQO – D_DQ15
DQ0 – DQ15
D-ADDR0 – D_ADDR13
38 CLK
86
D_CLK
16 WE
80
D_WEN
18 RAS
81
D_RASN
17 CAS
82
D_CASN
39 UDQM
88
D_UDQM
15 LDQM
89
D_LDQM
71, 68, 66, 64,
65, 67, 70, 72, 74,
77, 73, 79, 78, 75
19 – 22,
29 – 24,
18, 17
21 – 24,
27 – 32,
20, 19
A0 – A11, BA0, BA1
SD-RAM
IC503
23 – 26, 29 – 34,
22, 35, 20, 21
H_DQ0 – H_DQ15
25, 23, 22, 16 – 11,
9 – 5, 3, 2
RFSACD
7
SACD BUS
15
AGCINP
35
DATA0 – DATA15
DATA0 – DATA15
ADDR1 – ADDR7
1, 128 – 123
ADDR1 – ADDR7
SA_IRQ
I2S_DATA_OUT
SA_CS
I2S_BCLK_OUT
I2S_BFLAG_OUT
I2S_WCK_OUT
I2S_SYNC_OUT
FUR_RST
B_DATA/BE_DAT0
45
H_CSN
24
B_BCLK/SDCLK
46
B_FLAG/SERR
42
B_WCLK/SENB
44
B_SYNC/SYNC
RESETN
SACD, I2S
14
43
512FS_SACD
27M_SACD
122
SA_WAIT
SA_RW
H_IRQN
28
SYS_CLK
21
H_PROCCLOCK
18
AUD_CLK
29
H_WAIT
27
H_RWN
26
H_A1 – H_A6,
H_A_SEL
PCM_FLFRO
PCM_SLSRO
PCM_CSWO
PCM_DLDRO
PCM AUDIO
18
DSD AUDIO
19
HDMI AUDIO
17
PCM_LRCK
PCM_SCLK
DSD0_PCM
DSD1_PCM
DSD2_PCM
DSD3_PCM
DSD5_PCM
DSD4_PCM
DSD11_PCM
DSD9_PCM
DSD8_PCM
SWITCHING
IC553
WAVE SHAPER
Q481
OPTICAL
TRANSCEIVER
IC490
J481
COAXIAL
OPTICAL
DIGITAL OUT
PCM/DTS/
DOLBY DIGITAL
2, 3, 5, 6, 8,
9, 11, 12, 39 ,
40, 42, 43, 45,
46, 48, 49
2, 4, 5, 7, 8,
10, 11, 13, 42,
44, 45, 47, 48,
50, 51, 53
105, 103, 101
98, 96, 87, 93, 90,
91, 94, 95, 97, 100,
102, 104, 107
X903
27MHz
7
XTI
8
XTO
FSEL
FS_SEL
3
MO1
4
MO2
9
14
41
SPDIF_SW
40
AO1
D-FLIP FLOP
IC915
BE_RST
34
CLOCK GENERATOR
IC911
CPU-I/F
3
256FS_DAC
20
BE_RST
16
512FS_HDMI
21
SYS CLK
4
BE_RXD
27M_BE
27M_FE
512FS_BE
BE_BUSY
TMODE_SW
BE_BUSY 33
TMODE_SW 83
512FS_SACD
27M_SACD
512FS_AUDY
BE_RST
BE_RST
512FS_AUDY
BE_TXD
BE_CS
BE_RXD 46
BE_TXD 45
BE_CS 23
BUFFER
IC921
RESET SWITCH
IC401
SYSTEM CONTROLLER
IC404 (1/2)
: PLAY (AUDIO)
SIGNAL PATH
(Page 23)
(Page 23)
(Page 23)
(Page 23)
(Page 23)
(Page 23)
(Page 26)
(Page 25)
(Page 25)
(Page 25)
(Page 26)
(Page 23)
(Page 23)
(Page 23)
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