Sony DVP-M35 / DVP-S300 / DVP-S305 / DVP-S315 / DVP-S500D / DVP-S505D / DVP-S715 Service Manual ▷ View online
– 68 –
(Hysteresis)
(Hysteresis)
Pin
Signal Name
I/O
Type
Function
FG/PG counter
90
FGREF
I
TTL
FG counter reference pulse signal input. The polarity
of the input can also be checked by the host output
register (bit 10).
91
FGIN
I
TTL
FG pulse signal input. The polarity of the input can
also be checked by the host output register (bit 9).
92
PGREF
I
TTL
PG counter reference pulse signal input.
(Hysteresis)
93
PGIN
I
TTL
PG pulse signal input.
(Hysteresis)
JTAG pin
77
EMU0
I/O/Z
TTL
Emulator pin 0
(Internal pull-up)
76
EMU1
I/O/Z
TTL
Emulator pin 1
(Internal pull-up)
84
TRST
I
TTL
JTAG test reset pin
(Internal pull-up)
81
TMS
I
TTL
JTAG test mode select pin
(Internal pull-up)
78
TDO
O/Z
TTL
JTAG test data output pin
80
TDI
I
TTL
JTAG test data input pin
(Internal pull-up)
79
TCK
I/O
TTL
JTAG test clock
(Internal pull-up)
Other signal pins
95
CLKOUT1
O
COMS
Master clock output signal
94
RS
I
TTL
Reset input
(Internal pull-up)
65
X2/CLKIN
I
Oscillator
Internal oscillator input/clock input
66
X1
O
Oscillator
Internal oscillator output
31
TESTA
O
–
Reserved pin. Use without connecting.
Power supply pin
16, 55,
DVcc
–
–
+5V supply pin for digital circuit.
DGNO
–
–
Ground pin for digital circuit.
67, 83,
97
6, 15,
54, 64,
82, 85-
87, 96
– 69 –
Pin
Signal Name
I/O
Type
Function
AVcc
–
–
+5V supply pin for analog circuit.
AGND
–
–
Ground for analog circuit.
27, 30,
39, 48,
52
32, 35,
40, 47,
53
– 70 –
4-4. AC3 Decoder
MB86342 (MB-78 Board IC104)
4-4-1. Block Diagram
A-bus
P-bus
B-bus
MCLK1
XRST
MS
KFSIO
PSTOP
SYNC
MCLK2
SCKO
EXTIN
PM
FS1,FS2
HCLK
HDOUT
BST
GP0-GP7
HDIN
HCS
MOD
WE
D00-D19
CS
A00-A15
ICBRK
ICS0-ICS2
ICCLK
ICD0,ICD1
EXLOCK
LRCKI1
LRCKI2
BCKI1
BCKI2
SDI1,SDI2
LRCKO
BCKO
SDO0-SDO3
MCORE
MEM
CLKGM
ADIF
HISF
GP
EXMIF
EMUIF
LOG
– 71 –
4-4-2. Pin Functions
Pin No.
Signal Name
I/O
Function
5
MCLKI
I
Clock input pin
6
MCLK2
I/O
Clock input/output pin
1
XRST
I
Reset signal input
8
SCKO
O
System clock output pin
12
MS
I
Master/slave selection pin
L:Master (Crystal oscillation) H:Slave (External clock)
16
SYNC
I
Sync/async selection pin (L:Sync, H:Async)
2
EXTIN
I
System clock (384 fs) input pin
13, 14
FS1, FS2
I
Sampling frequency switching signal input pin
7
KFSIO
I/O
Audio clock (384 fs) input/output pin
9
PM
I
Test pin (normally set to GND.)
10
PSTOP
I
PLL/crystal oscillator control signal input pin
11
EXLOCK
I
Lock signal input pin
41
HCLK
I
Host interface clock input pin
43
HDIN
I
Host interface serial data input pin
44
HDOUT
O
Host interface serial data output pin
42
HCS
I
Host interface chip select input pin
45
BST
I
Normally fixed at “L”.
39-35, 32-30
GP0-GP7
I/O
8-bit general port input/output pin
17
LRCKI1
I/O
Sampling clock input/output pin for audio interface serial
data
18
BCKI1
I/O
Bit clock input/output pin for audio interface serial data
20
LRCKI2
I
Sampling clock input pin for audio interface serial data
21
BCK12
I
Bit clock input pin for audio interface serial data
19, 22
SDI1, SDI2
I
Serial data input pin for audio interface
23
LRCKO
O
Sampling clock output pin for audio interface serial data
24
BCKO
O
Bit clock output pin for audio interface serial data
25-27
SDO1-SDO3
O
Serial data output pin for audio interface
46
MOD
I
Pass mode control signal input pin
47
CS
O
Chip select output pin for external SRAM interface
48
WE
O
Write enable output pin for external SRAM interface
67-66,
64-55,
A00-A15
O
Serial data output pin for external SRAM interface
52-49
92, 91, 89-85
82-80,
D00-D19
I/O
Data input/output pin for external SRAM interface
77-68
93
ICCLK
O
Clock output pin for emulator
94
ICBRK
I
External brake control signal input pin for emulator
96, 95
ICD0, ICD1
I/O
Data/address input/output pin for emulator
99-97
ICS0-ICS2
O
Status output pin for emulator
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