Sony DVP-M35 / DVP-S300 / DVP-S305 / DVP-S315 / DVP-S500D / DVP-S505D / DVP-S715 Service Manual ▷ View online
– 64 –
Pin No.
Signal Name
120
SBD14
121
NC
122
SBD_13
123
VSS
124
SBD_12
125
SBD_11
126
SBD_10
127
VDD
128
SBD_9
129
SBD_8
130
SCLK
131
VSS
132
SBA_9
133
SBA_8
134
SBA_7
135
VDD
136
SBA_6
137
SBA_5
138
SBA_4
139
VSS
140
SBA_3
141
SBA_2
142
SBA_1
143
VDD
144
SBA_0
145
SBA_10
146
SBA_11
147
VSS
148
SCSI_N
149
SCS_N
150
SRAS_N
151
VDD
152
SRAS_N
153
SWE_N
154
SDQM
155
VSS
156
PLLVDD
157
NC
158
PLLVSS
159
VDD
160
NC
– 65 –
4-3. Digital Signal Processor CXD8730R (MB-78 Board IC506)
4-3-1. Pin Assignment
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
GI012
GI011
GI010
GI09
GI08
DGND
GI07
GI06
GI05/TMC1
GI04/TMC0
GI03/INT5
GI02/INT4
GI01/INT3
GI0/INT2
DGND
DVCC
AIN9
AIN8
AIN7
AIN6
AIN5
AIN4
AIN3
AIN2
AIN1
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
AIN0
AVCC
VRTA
VRTS
AVCC
TESTA
AGND
VRBS
VRBA
AGND
VRB3
VRT3
AOUT3
AVCC
AGND
AOUT2
VRT2
VRB2
VRB1
VRT1
AOUT1
AGND
AVCC
AOUT0
VRT0
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
GI013
GI014
GI015
DVCC
DGND
CLKOUT
RS
PGIN
PGREF
FGIN
FGREF
TRIN
TRREF
DGND
DGND
DGND
TRST
DVCC
DGND
TMS
TD1
TCK
TD0
EMU0
EMU1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PWM0
PWM1
PWM2
HCK/HLBS
HFS/HMR
HR/HRD
HX/HINT
SER/PAR
DVCO
X1
X2/CLKIN
DGND
HO0/HD0
HO1/HD1
HO2/HD2
HO3/HD3
HO4/HD4
HO5/HD5
HO6/HD6
HO7/HD7
DVCC
DGND
AGND
AVCC
VRB0
– 66 –
4-3-2. Pin Functions
This section describes signals. The input/output states of signals are differentiated by the input (I), output
(O), and high impedance (Z). Each signal is grouped by function.
Pin
Signal Name
I/O
Type
Function
Analog signal pin
29
VRTS
O
Analog
AD upper limit reference voltage output. When using
3.75V for the upper limit reference voltage, connect
the VRTS output to the VRTA input.
28
VRTA
I
Analog
AD upper limit reference voltage input.
33
VRBS
O
Analog
AD lower limit reference voltage output. When using
1.25V for the lower limit reference voltage, connect
the VRBS output to the VRBA input.
34
VRBA
I
Analog
AD lower limit reference voltage input.
26-27
AIN0-AIN9
I
Analog
Analog data input signal. Analog signal input to the
8-bit AD converter. The input to the AD converter is
switched automatically by the analog switch.
49
AOUT0
O
Analog
DAC0 buffer output signal. DAC0 buffer output. The
power down mode can be selected.
50
VRT0
I
Analog
DAC0 buffer upper limit reference voltage input.
51
VRB0
I
Analog
DAC0 buffer lower limit reference voltage input.
46
AOUT1
O
Analog
DAC1 buffer output signal. DAC1 buffer output. The
power down mode can be selected.
45
VRT1
I
Analog
DAC1 buffer upper limit reference voltage input.
44
VRB1
I
Analog
DAC1 buffer lower limit reference voltage input.
41
AOUT2
O
Analog
DAC2 buffer output signal. DAC2 buffer output. The
power down mode can be selected.
42
VRT2
I
Analog
DAC1 buffer upper limit reference voltage input.
43
VRB2
I
Analog
DAC2 buffer upper limit reference voltage input.
38
AOUT3
O
Analog
DAC3 buffer output signal. DAC3 buffer output. The
power down mode can be selected.
37
VRT3
I
Analog
DAC2 buffer upper limit reference voltage input.
36
VRB3
I
Analog
DAC3 buffer lower limit reference voltage input.
PWM pin
75-73 PWM0-PWM2
O
CMOS
PWM output signal. 8-bit PWM output. The output
pulse width can be set any value.
Host interface pin
68
SER/PAR
I
TTL
Host interface serial/parallel mode selection.
H:Serial, L:Parallel.
70
HR/HWR
I
TTL
Host serial data/host data read strobe signal input. In
the serial mode, the serial data is input. In the parallel
mode, the data read strobe signal is input.
(Internal pull-up)
– 67 –
HO6/HD6
8, 7,
5-1,
100-98
Pin
Signal Name
I/O
Type
Function
71
HFS/HWR
I
TTL
Frame sync signal/host data write strobe signal input
for data transmission. In the serial mode, the data
transmission frame sync signal is input. In the parallel
mode, the data write strobe signal is input.
69
HX/HINT
O/Z
CMOS
Host serial data/host interrupt signal output. In the
serial mode, the serial data is output. In the parallel
mode, the host interrupt signal is output.
72
HCK/HLBS
I
TTL
Clock/host low byte select signal input for host serial
data transmission. In the serial mode, the serial data
transmission clock is input. In the parallel mode, the
low byte select signal is input.
63-57
HO0/HD0-
I/O
TTL
General data output/parallel data input/output. In the
serial mode, the general data is output. In the parallel
mode, the parallel data is input/output.
56
HIO/HD7
I/O
TTL
General data/parallel data input/output. In the serial
mode, the general data is input/output. In the parallel
mode, the low byte select signal is input.
General input/output pin
14
GIO0/INT2
I/O
TTL
General data input/output/INT2 external interrupt
signal input. Selected by the interrupt control register.
13
GIO1/INT3
I/O
TTL
General data input/output/INT3 external interrupt
signal input. Selected by the interrupt control register.
12
GIO2/INT4
I/O
TTL
General data input/output/INT4 external interrupt
signal input. Selected by the interrupt control register.
11
GIO3/INT5
I/O
TTL
General data input/output/INT5 external interrupt
signal input. Selected by the interrupt control register.
10
GIO4/TMC0
I/O
TTL
General data input/output/timer 0 external clock
input. Selected by the timer control register.
9
GIO5/TMC1
I/O
TTL
General data input/output/timer 1 external clock
input. Selected by the timer control register.
GIO6-GIO15
I/O
TTL
General data input/output. The input/output is set by
the GIO control register. The input data is set to the
general input register. The data of the general output
register is output. When using a GIO from GIO0 to
GIO5 as the interrupt signal or input clock, be careful
not to set the corresponding control bit to the output
when changing the value of the GIO control register
value.
Track counter
88
TTREF
I
TTL
Track counter reference pulse signal input.
(Hysteresis)
89
TRIN
I
TTL
Track pulse signal input.
(Hysteresis)
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