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Model
DVP-M35 DVP-S300 DVP-S305 DVP-S315 DVP-S500D DVP-S505D DVP-S715
Pages
78
Size
858.68 KB
Type
PDF
Document
Service Manual
Brand
Device
DVD / OPERATION MANUAL
File
dvp-m35-dvp-s300-dvp-s305-dvp-s315-dvp-s500d-dvp-s.pdf
Date
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Sony DVP-M35 / DVP-S300 / DVP-S305 / DVP-S315 / DVP-S500D / DVP-S505D / DVP-S715 Service Manual ▷ View online

– 56 –
4.
IC PIN DESCRIPTION
4-1. ARP
CXD1865R (IC806 on MB-78 board)
4-1-1.
Block Diagram
ADC
DAC
VCO
O p e -
a m p l i f i e r
C l o c k  
c o n t r o l
C L V   c o n t r o l  
s i g n a l  
g e n e r a t i o n
R F   s i g n a l  
p r o c e s s i n g
EFM/EFM+ 
demodulation
F r a m e / s e c t o r  
s y n c   a d d r e s s  
p r o t e c t i o n
B u f f e r  
m e m o r y
  c o n t r o l
O u t p u t  
c o n t r o l
C D D A  
s i g n a l  
processing
E C C   c o r e
B u i l t - i n  
m e m o r y
C P U   I / F
10:RFIN1
12:RFIN2
19:AOUT
27:Y
35:VCOIN
122:MCKI
124:SCKI
2:PLCKO
31:INM
32:INP
43:MDS0
46:MDS1
48:MDP0
49:MDP1
47:MON
53:LOCK
56:XWR
57:XRD
59–62, 64–67:D0–D7
70–73, 75–78:A0–A7
80:XINT
81:XCS
83:XWAT
84:XRST
106:DATA
107:BCLK
108:LRCK
109:DOUT
110:MUTE
112:MD2
90:SDCK
91:XSHD
92:XSRO
93:XSAK
94:SDEF
96–99, 101–104:SD0–SD7
137–139, 141–143,
145–147, 149:MA0–MA9
150:XMWR
151:XCAS
153:XRAS
154:XOE
156–159, 161–164,
166–169, 171–174:MD00–MD15
113:WFCK
114:SCOR
116:EXCK
117:SBSO
119:SOSO
120:SOCK
55:FWON
50:DFCT
51:NORF
52:JITPWM
– 55 –
– 57 –
4-1-2. Pin Functions
Pin No.
Signal Name
Direction
Level
Function
1
PLCKI
I
3.3
PLCK input
2
PLCKO
O
3.3
PLCK output
3
VSS
P
Digital ground
4
RFD
B
3.3
RF2 value data input/output
5
VDD
P
3.3
Digital positive power supply
6
VSS1
ADP
Digital ground
7
VRB
AI
ADC reference
8
VRBS
AI
ADC reference
9
GNDA1
AP
Analog ground
10
RFIN1
AI
RF input
11
AIN
AI
RF input
12
RFIN2
AI
RF input
13
VCCA1
AP
5
Analog positive power supply
14
VRTS
AI
ADC reference
15
VRT
AI
ADC reference
16
VDD1
ADP
5
Digital positive power supply
17
VSS2
ADP
Digital ground
18
VDD2
ADP
3.3
Digital positive power supply
19
AOUT
AO
DAC output
20
VCCA2
AP
3.3
Analog positive power supply
21
IREF
AI
DAC reference current
22
VREF
AI
DAC reference voltage
23
COMP
AI
DAC compensation pin
24
BIAS
AI
DAC bias pin
25
GNDA2
AP
Analog ground
26
VCCA3
AP
3.3
Analog positive power supply
27
Y
AO
Ope-amplifier output
28
FR1
AO
Feedback resistance switching 1
29
FR2
AO
Feedback resistance switching 2
30
FR3
AO
Feedback resistance switching 3
31
INM
AI
Ope-amplifier negative input
32
INP
AI
Ope-amplifier positive input
33
GNDA3
AP
Analog ground
34
GNDA4
AP
Analog ground
35
VCOIN
AI
VCC control input
36
R1
AI
VCO external resistor 1
37
R2
AI
VCO external resistor 2
38
TEST0
AO
VCO test output
39
VCCA4
AP
Analog positive power supply
40
VCK
B
3.3
VCO oscillation output/test input
– 58 –
Pin No.
Signal Name
Direction
Level
Function
41
VSS
P
Digital ground
42
TESTA
I
3.3
Test pin
43
MDSO
O
5
CLV speed error
44
VDD
P
3.3
Digital positive power supply
45
VSS
P
Digital ground
46
MDS1
O
5
CLV speed error
47
MON
O
5
Motor on
48
MDP0
O
5
CLV phase error
49
MDP1
O
5
CLV phase error
50
DFCT
O
5
Defect detection output
51
NORF
O
5
NO RF detection output
52
JITPWM
O
5
Jitter PWM output
53
LOCK
O
5
EFM lock output
54
VDDS
P
Digital positive power supply
55
FWON
I
5
Sync protection on
56
XWR
I
3.3
CPU write
57
XRD
I
3.3
CPU read
58
VDD
P
3.3
Digital positive power supply
59
D0
B
5
CPU data
60
D1
B
5
CPU data
61
D2
B
5
CPU data
62
D3
B
5
CPU data
63
VSS
P
Digital ground
64
D4
B
5
CPU data
65
D5
B
5
CPU data
66
D6
B
5
CPU data
67
D7
B
5
CPU data
68
VDDS
P
5
Digital positive power supply
69
TEST
I
5
Test pin
70
A0
I
5
CPU address
71
A1
I
5
CPU address
72
A2
I
5
CPU address
73
A3
I
5
CPU address
74
SCEN(!)
I
3.3
75
A4
I
5
CPU address
76
A5
I
5
CPU address
77
A6
I
5
CPU address
78
A7
I
5
CPU address
79
VDD
P
3.3
Digital positive power supply
80
XINT
OD
5
Interruption
81
XCS
I
5
Chip select
82
VSS
P
Digital ground
– 59 –
Pin No.
Signal Name
Direction
Level
Function
83
XWAT
OD
5
Wait
84
XRST
I
5
Reset
85
VDD
P
3.3
Digital positive power supply
86
TEST0
I
3.3
Test pin
87
SCMD
I
3.3
Test pin
88
ETST
I
3.3
Test pin
89
VSS
Digital ground
90
SDCK
O
3.3
SD bus clock
91
XSHD
O
3.3
SD bus header
92
XSRQ
I
3.3
SD bus REQ
93
XSAK
O
3.3
SD bus ACK
94
SDEF
O
3.3
SD bus error flag
95
VDD
P
3.3
Digital positive power supply
96
SDO
O (B)
3.3
SD bus data
97
SD1
O (B)
3.3
SD bus data
98
SD2
O (B)
3.3
SD bus data
99
SD3
O (B)
3.3
SD bus data
100
VSS
P
Digital ground
101
SD4
O (B)
3.3
SD bus data
102
SD5
O (B)
3.3
SD bus data
103
SD6
O (B)
3.3
SD bus data
104
SD7
O (B)
3.3
SD bus data
105
VDD
P
3.3
Digital positive power supply
106
DATA
O
3.3
CDDA data
107
BCLK
O
3.3
CDDA bit clock
108
LRCK
O
3.3
CDDA LR clock
109
DOUT
O
3.3
Digital out
110
MUTE
I
5
Audio mute
111
VSS
P
Digital ground
112
MD2
I
5
Digital out on
113
WFCK
O
5
Frame clock
114
SCOR
O
5
Subcode sync
115
VDDS
P
5
Digital positive power supply
116
EXCK
I
5
SBSO reading clock
117
SBSO
O
5
SubP to W serial output
118
VSS
P
Digital ground
119
SQSO
O
5
SubQ serial output
120
SQCK
I
5
SBSO reading clock
121
VSS
P
Digital ground
122
MCKI
I
5
ECC clock
123
VDDS
P
5
Digital positive power supply
124
SCKI
I
5
System clock
Page of 78
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