Sony DVP-M35 / DVP-S300 / DVP-S305 / DVP-S315 / DVP-S500D / DVP-S505D / DVP-S715 Service Manual ▷ View online
– 60 –
Pin No.
Signal Name
Direction
Level
Function
125
VSS
P
Digital ground
126
MNT0
B
3.3
Monitor bus
127
MNT1
B
3.3
Monitor bus
128
MNT2
B
3.3
Monitor bus
129
MNT3
B
3.3
Monitor bus
130
VDD
P
3.3
Digital positive power supply
131
MNT4
B
3.3
Monitor bus
132
MNT5
B
3.3
Monitor bus
133
MNT6
B
3.3
Monitor bus
134
MNT7
B
3.3
Monitor bus
135
ESTB
O
3.3
Error information strobe
136
VSS
P
Digital ground
137
MA0
O
3.3
DRAM address
138
MA1
O
3.3
DRAM address
139
MA2
O
3.3
DRAM address
140
VDD
P
3.3
Digital positive power supply
141
MA3
O
3.3
DRAM address
142
MA4
O
3.3
DRAM address
143
MA5
O
3.3
DRAM address
144
VSS
P
Digital ground
145
MA6
O
3.3
DRAM address
146
MA7
O
3.3
DRAM address
147
MA8
O
3.3
DRAM address
148
VDD
P
3.3
Digital positive power supply
149
MA9
O
3.3
DRAM address
150
XMWR
O
3.3
DRAM write enable
151
XCAS
O
3.3
DRAM CAS
152
VSS
P
Digital ground
153
XRAS
O
3.3
DRAM RAS
154
XOE
O
3.3
DRAM output enable
155
VDD
P
3.3
Digital positive power supply
156
MD00
B
3.3
DRAM data
157
MD01
B
3.3
DRAM data
158
MD02
B
3.3
DRAM data
159
MD03
B
3.3
DRAM data
160
VSS
P
Digital ground
161
MD04
B
3.3
DRAM data
162
MD05
B
3.3
DRAM data
163
MD06
B
3.3
DRAM data
164
MD07
B
3.3
DRAM data
165
VDD
P
3.3
Digital positive power supply
166
MD08
B
3.3
DRAM data
– 61 –
Pin No.
Signal Name
Direction
Level
Function
167
MD09
B
3.3
DRAM data
168
MD10
B
3.3
DRAM data
169
MD11
B
3.3
DRAM data
170
VSS
P
Digital ground
171
MD12
B
3.3
DRAM data
172
MD13
B
3.3
DRAM data
173
MD14
B
3.3
DRAM data
174
MD15
B
3.3
DRAM data
175
PLDIR
I
3.3
PLCK direction control
176
VSS
P
Digital ground
*Function of direction
I [input], O [output], OD [output (open drain)], O(B) [output (bi-direction during test)],
B[input/output (bi-direction)], P [power supply], ADP [power supply (digital for analog cell)],
AP [power supply (analog)].
AI [input (analog)], AO [output (analog)]
– 62 –
4-2. AV Decoder L64020 (MB-78 Board IC203)
4-2-1. Block Diagram
Host I/F Block
Audio Decoder Block
Display Controller
Block
27MHz
1/300
CK
Divider
SCR
Counter
A/V Sync
Timing Gen
MPEG-2
Dolby AC-3
Linear PCM
MPU I/F
Programmable
System
Pre-Parser
CPU
PES/ES MPEG-2
Program Stream
Data Strobe
Data Request
SDRAM Interface
SDRAM x 2 (1M x 16 Bit = 1 Chip)
SW
(MUX)
Bypass
I
/F
A/V AMP or
AC-3 Decoder
NTSC/PAL
Encoder
Display
Controller
CCIR601
Sync
DAC
MIX
Filters
OSD/SPU
MPEG-2
Video
Decoder
– 63 –
4-2-2. Pin Assignment
Pin No.
Signal Name
1
VSS
2
SBD_7
3
SBD_6
4
SBD_5
5
SBD_4
6
VDD
7
SBD_3
8
SBD_2
9
SBD_1
10
SBD_0
11
VSS
12
CH_DATA_0
13
CH_DATA_1
14
CH_DATA_2
15
CH_DATA_3
16
CH_DATA_4
17
CH_DATA_5
18
CH_DATA_6
19
CH_DATA_7
20
VSS
21
TOS_N
22
NC
23
NC
24
ERROR_N
25
VDD
26
AVALID_N
27
VVALID_N
28
DCK
29
VREQ_N
30
AREQ_N
31
NC
32
NC
33
VSS
34
A_8
35
A_7
36
A_6
37
A_5
38
A_4
39
A_3
40
VDD
Pin No.
Signal Name
41
NC
42
VDD
43
A_2
44
A_1
45
A_0
46
VSS
47
D_7
48
D_6
49
D_5
50
D_4
51
D_3
52
D-2
53
D-1
54
D-0
55
VSS
56
SYSCLK
57
RESET_N
58
DREQ_N
59
INTR_N
60
BUSMODE
61
VDD
62
DTACK_N/
RDY_N
63
READ/READ_N
64
DS_N/WRITE_N
65
WAIT_N/WTN
66
VSS
67
AS_N
68
CS_N
69
VS
70
HS
71
VDD
72
OSD_ACTIVE
73
PD_0
74
PD_1
75
VSS
76
PD_2
77
PD_3
78
PD_4
79
VDD
Pin No.
Signal Name
80
NC
81
VSS
82
PD_5
83
PD_6
84
PD_7
85
VSS
86
BLANK
87
CREF
88
EXT_OSD_0
89
EXT_OSD_1
90
EXT_OSD_2
91
EXT_OSD_3
92
NC
93
VDD
94
ACLK_441
95
ACLK_48
96
ACLK_32
97
VSS
98
CD_BLK
99
CD_LRCLK
100
CD_ALCK
101
CD_ASDATA
102
SPDIF_N
103
A_ACLK
104
VDD
105
BCLK
106
LRCLK
107
ASDATA
108
NC
109
NC
110
VSS
111
SPDIF_OUT
112
AUDIO_SYNC
113
TM1
114
TM0
115
ZTEST
116
SCAN_TE
117
PREQ_N
118
VDD
119
SBC_15
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