Sony AVD-S500ES Service Manual ▷ View online
37
AVD-S500ES
• IC1036 CXD2753R (DSD DECODER) (MB Board (7/12))
Pin No.
Pin Name
I/O
Pin Description
1
VSCA0
—
Ground pin (for core)
2
XMSLAT
I
Serial data latch pulse signal input from the machanism controller
3
MSCK
I
Serial data transfer clock signal input from the mechanism controller
4
MSDATI
I
Serial data input from the mechanism controller
5
VDCA0
—
Power supply pin (+2.5 V) (for core)
6
MSDATO
O
Serial data output to the mechanism controller
7
MSREADY
O
Ready signal output to the mechanism controller “L”: ready
8
XMSDOE
O
Serial data output enable signal output pin Not used. (Open)
9
XRST
I
Reset signal input from the mechanism controller “L”: reset
10
SMUTE
I
Soft muting on/off control signal input from the mechanism controller
“H”: muting on
11
MCKI
I
Master clock signal (33.8688 MHz) input
12
VSIOA0
—
Ground pin (for I/O)
13
EXCKO1
O
Master clock signal (33.8688 MHz) output to the digital audio processor
14
EXCKO2
O
External clock 2 signal output Not used. (Open)
15
LRCK
O
L/R sampling clock signal (44.1 kHz) output Not used. (Open)
16
F75HZ
O
Not used. (Open)
17
VDIOA0
—
Power supply pin (+3.3 V) (for I/O)
18 to 25
MNT0 to MNT7
O
Monitor signal output Not used. (Open)
26
TCK
I
Clock signal input from the DVD system processor
27
TDI
I
Serial data input from the DVD system processor
28
VSCA1
—
Ground pin (for core)
29
TDO
O
Serial data output to the DVD system processor
30
TMS
I
TMS signal input from the DVD system processor
31
TRST
I
Reset signal input from the DVD system processor “L”: reset
32 to 34
TEST1 to TEST3
I
Input for the test (normally: fixed at L)
35
VDCA1
—
Power supply pin (+2.5 V) (for core)
36
UBIT
O
Not used. (Open)
37
XBIT
O
Not used. (Open)
38 to 41
SUPDT0 to SUPDT3
O
Supplementary data output Not used. (Open)
42
VSIOA1
—
Ground pin (for I/O)
43, 44
SUPDT4, SUPDT5
O
Supplementary data output Not used. (Open)
45
VDIOA1
—
Power supply pin (+3.3 V) (for I/O)
46, 47
SUPDT6, SUPDT7
O
Supplementary data output Not used. (Open)
48
SUPEN
O
Supplementary data enable signal output Not used. (Open)
49
VSCA2
—
Ground pin (for core)
50
NC
O
Not used. (Open)
51, 52
TEST4, TEST5
I
Input for the test (normally: fixed at L)
53
NC
O
Not used. (Open)
54
VDCA2
—
Power supply pin (+2.5 V) (for core)
55, 56
DSADML, DSADMR
O
Not used. (Open)
57
BCKASL
I
Input/output selection signal input of bit clock signal (2.8224 MHz) for DSD data
output “L”: input (slave), “H”: output (master) Fixed at H in this set
58
VSDSD0
—
Ground pin (for DSD data output)
59
BCKAI
I
Bit clock signal (2.8224 MHz) input for DSD data output Not used. (Open)
60
BCKAO
O
Bit clock signal (2.8224 MHz) output for DSD data output
61
PHREFI
I
Bit clock signal (2.8224 MHz) input for DSD data output Not used. (Open)
62
PHREFO
O
Bit clock signal (2.8224 MHz) output to the digital audio processor Not used. (Open)
63
ZDFL
O
Front L-ch Zero data flag detection signal output Not used. (Open)
64
DSAL
O
Front L-ch DSD data output to the digital audio processor
65
ZDFR
O
Front R-ch Zero data flag detection signal output Not used. (Open)
66
DSAR
O
Front R-ch DSD data output to the digital audio processor
38
AVD-S500ES
Pin No.
Pin Name
I/O
Pin Description
67
VDDSD0
—
Power supply pin (+3.3 V) (for DSD data output)
68
ZDFC
O
Center zero data flag detection signal output Not used. (Open)
69
DSAC
O
Center DSD data output to the digital audio processor
70
ZDFLFE
O
Woofer zero data flag detection signal output Not used. (Open)
71
DSALFE
O
Woofer DSD data output to the digital audio processor
72
VSDSD1
—
Ground pin (for DSD data output)
73
ZDFLS
O
Rear L-ch zero data flag detection signal output Not used. (Open)
74
DSALS
O
Rear L-ch DSD data output to the digital audio processor
75
ZDFRS
O
Rear R-ch zero data flag detection signal output Not used. (Open)
76
DSARS
O
Rear R-ch DSD data output to the digital audio processor
77
VDDSD1
—
Power supply pin (+3.3 V) (for DSD data output)
78, 79
IOUT0, IOUT1
O
Data output for IEEE 1394 link chip interface Not used. (Open)
80
VSCB0
—
Ground pin (for core)
81, 82
IOUT2, IOUT3
O
Data output for IEEE 1394 link chip interface Not used. (Open)
83
VDCB0
—
Power supply pin (+2.5 V) (for core)
84, 85
IOUT4, IOUT5
O
Data output for IEEE 1394 link chip interface Not used. (Open)
86
VSIOB0
—
Ground pin (for I/O)
87
IANCO
O
Transmission information data output for IEEE 1394 link chip interface
Not used. (Open)
88
IFULL
I
Data transmission hold request signal input for IEEE 1394 link chip interface
Not used. (Connected to ground.)
89
IEMPTY
I
High speed transmission request signal input for IEEE 1394 link chip interface
Not used. (Connected to ground.)
90
VDIOB0
—
Power supply pin (+3.3 V) (for I/O)
91
IFRM
O
Frame reference signal output for IEEE 1394 link chip interface Not used. (Open)
92
IOUTE
O
Enable signal output for IEEE 1394 link chip interface Not used. (Open)
93
IBCK
O
Data transmission clock signal output for IEEE 1394 link chip interface
Not used. (Open)
94
VSCB1
—
Ground pin (for core)
95
IERR
I
Not used. (Fixed at H in this set.)
96
IANCI
I
Not used. (Fixed at L in this set.)
97
IPLAN
I
Not used. (Fixed at H in this set.)
98
IHOLD
O
Not used. (Open)
99
VDCB1
—
Power supply pin (+2.5 V) (for core)
100
IVLD
I
Not used. (Fixed at L in this set.)
101 to 105
IDIN0 to IDIN4
I
Not used. (Fixed at L in this set.)
106
VSIOB1
—
Ground pin (for I/O)
107 to 109
IDIN5 to IDIN7
I
Not used. (Fixed at L in this set.)
110
VDIOB1
—
Power supply pin (+3.3 V) (for I/O)
111 to 114
WAD0 to WAD3
I
External A/D data input for PSP physical disc mark detection Not used. (Open)
115
TESTI
I
Input for the test (normally: fixed at L)
116
VSCB2
—
Ground pin (for core)
117 to 120
WAD4 to WAD7
I
External A/D data input for PSP physical disc mark detection Not used. (Open)
121
VDCB2
—
Power supply pin (+2.5 V) (for core)
122
WRFD
I
Not used. (Fixed at L in this set.)
123
WCK
I
Operation clock signal input for PSP physical disc mark detection from the DVD
decoder
124, 125
WAVDD0, WAVDD1
—
A/D power supply pin (+2.5 V) (for PSP physical disc mark detection)
126
WARFI
I
Analog RF signal input for PSP physical disc mark detection from the DVD/CD RF
amplifier
127
WAVRB
I
A/D bottom reference pin for PSP physical disc mark detection
128, 129
WAVSS0, WAVSS1
—
A/D ground pin (for PSP physical disc mark detection)
130
VSIOA2
—
Ground pin (for I/O)
39
AVD-S500ES
Pin No.
Pin Name
I/O
Pin Description
131 to 134
DQ7 to DQ4
I/O
Two-way data bus with the SD-RAM
135
VDIOA2
—
Power supply pin (+3.3 V) (for I/O)
136 to 139
DQ3 to DQ0
I/O
Two-way data bus with the SD-RAM
140
VSIOA3
—
Ground pin (for I/O)
141
DCLK
O
Clock signal output to the SD-RAM
142
DCKE
O
Clock enable signal output to the SD-RAM
143
XWE
O
Write enable signal output to the SD-RAM
144
XCAS
O
Column address strobe signal output to the SD-RAM
145
XRAS
O
Row address strobe signal output to the SD-RAM
146
VDIOA3
—
Power supply pin (+3.3 V) (for I/O)
147
NC
O
Not used. (Open)
148, 149
A11, A10
O
Address signal output to the SD-RAM
150
VSCA3
—
Ground pin (for core)
151, 152
A9, A8
O
Address signal output to the SD-RAM
153
VDCA3
—
Power supply pin (+2.5 V) (for core)
154 to 157
A7 to A4
O
Address signal output to the SD-RAM
158
VSIOA4
—
Ground pin (for I/O)
159 to 162
A3 to A0
O
Address signal output to the SD-RAM
163
VDIOA4
—
Power supply pin (+3.3 V) (for I/O)
164
XSRQ
O
Serial data request signal output to the DVD decoder
165
XSHD
I
Header flag signal input from the DVD decoder
166
SDCK
I
Serial data transfer clock signal input from the DVD decoder
167
XSAK
I
Serial data effect flag signal input from the DVD decoder
168
SDEF
I
Error flag signal input from the DVD decoder
169 to 176
SD0 to SD7
I
Stream data signal input from the DVD decoder
40
AVD-S500ES
• IC1029 CXP973064-232R (MECHANISM CONTROL) (MB Board (8/12))
Pin No.
Pin Name
I/O
Pin Description
1
EEP_SO
O
Not used. (Open)
2
SDEN
O
Serial data enable signal output
3
DOCTRL/ISBTEST
O
Digital out ON/OFF control signal output
4
DSD_XRST
O
DSD reset signal output
5
EEP_SI
I/O
Data bus signal input from/output to EEPROM IC.
6
EEP_RDY
I
EEPROM ready signal input
7
FCS_JMP_1
O
Focus jump 1 signal output to focus/tracking coil driver, spindle/sled motor driver IC.
8
FCS_JMP_2
O
Focus jump 2 signal output to focus/tracking coil driver, spindle/sled motor driver IC.
9
SENS_CD
I
Internal status (SENSE) signal input
10
CD-DVD-XTSEL
O
CD spectrum signal output to CD decoder, digital servo processor IC.
11
NON
O
Not used. (Open)
12
XCS_DVD
O
Chip select signal output to DVD decoder IC.
13
VSS
—
Ground pin
14 to 21
D0 to D7
I/O
Two-way data bus signal input from/output to DVD decoder IC.
22, 23
INIT0_DVD, INIT1_DVD
I
Interrupt signal input from DVD decoder IC.
24
MSCK_SAMBA
O
Serial clock signal output
25
XRST_1882
O
Reset signal output to DVD decoder IC.
26
SCOR
I
Subcode sync (S0+S1) detection signal input from CD decoder, digital servo processor
IC.
27
LAT_CD
O
Serial data latch pulse signal output to CD decoder, digital servo processor IC.
28
LDON
O
Laser diode ON/OFF control signal output
29
MIRR
I
Mirror signal input
30
COUT_CD
I
Numbers of track counted signal input
31
INLIM
I
Detection signal input from limit in switch. The optical pick-up is inner position when
H.
32
CS_ZIVA
O
Chip select signal output to DVD system processor IC.
33
SI_ZIVA
I
Serial data input from DVD system processor IC.
34
SO_ZIVA
O
Serial data output to DVD system processor IC.
35
SCK_ZIVA
O
Serial data transfer clock signal output to DVD system processor IC.
36
DRVIRQ
O
Interrupt request signal output to DVD system processor IC.
37
DRVRDY
O
Ready signal output to DVD system processor IC.
38
RST
I
System reset signal input from DVD system processor IC.
39
VSS
—
Ground pin
40
XTAL
I
System clock input (20 MHz)
41
EXTAL
O
System clock output (20 MHz)
42
VDD
—
Power supply pin (+3.3 V)
43, 44
SLED_A, SLED_B
O
Sled motor drive signal output to focus/tracking coil driver, spindle/sled motor driver
IC.
45
SCK_DSD
O
Clock signal output to DVD decoder IC.
46
SDOUT_DSD
O
Serial data output to DSD decoder IC
47
SDIN_DSD
I
Serial data input from DSD decoder IC
48
READY_DSD
I
Ready signal output to DSD decoder IC
49
DATA_CD
O
Serial data output to CD decoder, digital servo processor IC.
50
CLOK_CD
O
Serial data transfer clock signal output to CD decoder, digital servo processor IC.
51
XMSLAT
O
Serial data latch pulse signal output to DSD decoder IC
52
SQSO
I
Subcode Q data input from DVD decoder IC.
53
MUTE_DSD
O
Soft muting on/off control signal output to DSD decoder IC
54
SQCK
O
Subcode Q data reading clock signal output to DVD decoder IC.
55
VSS
—
Ground pin
56, 57
TRAY IN, TRAY OUT
I
Not used. (Fixed at L in this set.)
58
GFS_DVD
I
Guard frame sync signal input from DVD decoder IC.
59
MUTE_CD
O
Muting ON/OFF control signal output to CD decoder, digital servo processor IC.
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