Sony AVD-S500ES Service Manual ▷ View online
29
AVD-S500ES
Pin No.
Pin Name
I/O
Pin Description
171
CDM-LP
O
CDM tray open signal output for roulette
172
CDM-LN
O
CDM tray close signal output for roulette
173
XCDM-OPEN
I
CDM tray open end detect (S0) signal input
174
NO-USE
—
Not used. (Open)
175
VSS
—
Ground pin
176
VCC
—
Power supply pin (+3.3 V)
30
AVD-S500ES
• IC1011 CXD9718Q (AUDIO DIGITAL SIGNAL PROCESSOR) (MB Board (3/12))
Pin No.
Pin Name
I/O
Pin Description
1
VSS
—
Ground pin
2
XRST
I
System reset signal input from the system controller “L”: reset
3
EXTIN
I
Master clock signal input Not used. (Connect to ground.)
4
LRCKI3
I
Sampling frequency selection signal input Not used. (Connect to ground.)
5
VDDI
—
Power supply pin (+2.5 V)
6
BCKI3
I
Sampling frequency selection signal input Not used. (Connect to ground.)
7
PLOCK
O
Internal PLL lock signal output Not used. (Open)
8
VSS
—
Ground pin
9
MCLK1
I
System clock input (13.5 MHz)
10
VDDI
—
Power supply pin (+2.5 V)
11
VSS
—
Ground pin
12
MCLK2
O
System clock output (13.5 MHz)
13
MS
I
Master/slave setting pin “L”: internal clock, “H”: external clock
Fixed at “L” in this set
14
SCKOUT
O
Internal system clock output
15
LRCKI1
I
L/R sampling clock signal (44.1 kHz) input from the A/D converter and digital audio
interface receiver
16
VDDE
—
Power supply pin (+3.3 V)
17
BCKI1
I
Bit clock signal (2.8224 MHz) input from the A/D converter and digital audio
interface receiver
18
SDI1
I
Audio serial data input from the A/D converter
19
LRCKO
O
L/R sampling clock signal (44.1 kHz) output to the audio digital signal processor
20
BCKO
O
Bit clock signal (2.8224 MHz) output to the audio digital signal processor
21
VSS
—
Ground pin
22
KFSIO
I
Audio clock signal input from the digital audio interface receiver
23 to 26
SDO1 to SDO4
O
Audio serial data output to the audio digital signal processor
27
SPDIF
O
SPDIF signal output Not used. (Open)
28
LRCKI2
I
L/R sampling clock signal (44.1 kHz) input from the A/D converter and digital audio
interface receiver
29
BCKI2
I
Bit clock signal (2.8224 MHz) input from the A/D converter and digital audio
interface receiver
30
SDI2
I
Audio serial data input from the digital audio interface receiver
31
VSS
—
Ground pin
32
HACN
O
Acknowledge signal output to the system controller
33
HDIN
I
Serial data input from the system controller
34
HCLK
I
Serial data transfer clock signal input from the system controller
35
HDOUT
O
Serial data output to the system controller
36
HCS
I
Chip select input from the system controller
37
GP12
I/O
GP data signal input/output terminal
38
GP13
I/O
GP data signal input/output terminal Not used. (Open)
39
GP14
I/O
GP data signal input/output terminal Not used. (Open)
40
VDDI
—
Power supply pin (+2.5 V)
41
VSS
—
Ground pin
42
GP15
I/O
GP data signal input/output terminal Not used. (Open)
43
OE0
O
Output terminal of data input/output mask Not used. (Open)
44
CS0
O
Chip select signal output pin
45
WE0
O
Write enable signal output pin
46
VDDE
—
Power supply pin (+3.3 V)
47
WMD1
I
External memory wait mode setting pin Fixed at “H” in this set
48
VSS
—
Ground pin
49
WMD0
I
External memory wait mode setting pin Fixed at “H” in this set
50
PAGE2
O
External memory page selection signal output pin Not used. (Open)
31
AVD-S500ES
Pin No.
Pin Name
I/O
Pin Description
51
VSS
—
Ground pin
52, 53
PAGE1, PAGE0
O
External memory page selection signal output Not used. (Open)
54
BOOT
I
Boot mode control signal input Not used. (Connect to ground.)
55
TST1
I
Test pin
56
BST
I
Boot strap signal input from the system controller
57
MOD1
I
Operation mode setting pin “L”: enhanced mode, “H”: normal mode
Fixed at “H” in this set
58
MOD0
I
Operation mode setting pin “L”: single chip mode, “H”: can not use
Fixed at “L” in this set
59
EXLOCK
I
PLL lock error signal and data error flag input from the digital audio interface receiver
60
VDDI
—
Power supply pin (+2.5 V)
61
VSS
—
Ground pin
62, 63
A17, A16
O
Address signal output Not used. (Open)
64 to 66
A15 to A13
O
Address signal output
67
GP10
—
Not used. (Open)
68
GP9
O
Audio signal output to the system controller
69
GP8
I
Channel status bit 1 input from the digital audio interface receiver
70
VDDI
—
Power supply pin (+2.5 V)
71
VSS
—
Ground pin
72 to 75
D15/GP7 to D12/GP4
I/O
Two-way data bus signal input/output
76
VDDE
—
Power supply pin (+3.3 V)
77 to 80
D11/GP3 to D8/GP0
I/O
Two-way data bus signal input/output
81
VSS
—
Ground pin
82 to 85
A9, A12 to A10
O
Address signal output
86
TDO
O
Simplicity emulation data output Not used. (Open)
87
TMS
I
Simplicity emulation data input start and end pin Not used. (Open)
88
XTRST
I
Simplicity emulation non-sync break signal input Not used. (Open)
89
TCK
I
Simplicity emulation clock signal input Not used. (Open)
90
TDI
I
Simplicity emulation data input Not used. (Open)
91
VSS
—
Ground pin
92 to 97
A8 to A3
O
Address signal output
98, 99
D7, D6
I/O
Two-way data bus input/output
100
VDDI
—
Power supply pin (+2.5 V)
101
VSS
—
Ground pin
102 to 105
D5 to D2
I/O
Two-way data bus input/output
106
VDDE
—
Power supply pin (+3.3 V)
107, 108
D1, D0
I/O
Two-way data bus input/output
109, 110
A2, A1
O
Address signal output
111
VSS
—
Ground pin
112
A0
O
Address signal output
113
PM
I
PLL initialize signal input from the system controller
114
SDI3
I
Audio serial data input
115
SDI4
I
Ground pin
116
SYNC
I
Sync/non-sync setting pin “L”: sync, “H”: non-sync Fixed at “H” in this set
117
TST2
—
Ground pin
118
GP11
—
Not used. (Open)
119
TST3
—
Ground pin
120
VDDI
—
Power supply pin (+2.5 V)
32
AVD-S500ES
• IC1025 CXD3068Q (DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR) (MB Board (5/12))
Pin No.
Pin Name
I/O
Pin Description
1
DVDD0
—
Power supply pin (+3.3 V) (digital system)
2
XRST
I
Reset signal input from mechanism controller IC “L”: reset
3
MUTE
I
Muting on/off control signal input from mechanism controller IC “H”: muting on
4
DATA
I
Serial data input from mechanism controller IC
5
XLAT
I
Serial data latch pulse signal input from mechanism controller IC
6
CLOK
I
Serial data transfer clock signal input from mechanism controller IC
7
SENS
O
Internal status (SENSE) signal output to mechanism controller IC
8
SCLK
I
SENSE serial data reading clock signal input from mechanism controller IC
9
ATSK
I/O
Input/output for anti-shock Not used. (Fixed at L in this set.)
10
WFCK
O
Write frame clock signal output to DVD decoder IC
11
RFCK
O
RFCK signal output Not used. (Open)
12
XPCK
O
XPCK signal output Not used. (Open)
13
GFS
O
Guard frame sync signal output to mechanism controller IC
14
C2PO
O
C2 pointer signal output to DVD decoder IC
15
SCOR
O
Subcode sync (S0+S1) detection signal output to DVD decoder IC and mechanism
controller IC
16
C4M
O
4.2336 MHz clock signal output Not used. (Open)
17
WDCK
O
Guard subcode sync (S0+S1) detection signal output to DVD decoder IC
18
DVSS0
—
Ground pin (digital system)
19
COUT
O
Numbers of track counted signal output to mechanism controller IC
20
MIRR
O
Mirror signal output to mechanism controller IC
21
DFCT
I/O
Defect signal input/output Not used.
22
FOK
O
Focus OK signal output to mechanism controller IC
23
PWMI
I
Spindle motor external control signal input Not used. (Fixed at L in this set.)
24
LOCK
O
GFS is sampled by 460 Hz “H” output when GFS is “H”.
25
MDP
O
Spindle motor servo drive signal output to DVD decoder IC
26
SSTP
I
Detection signal input from limit in switch
The optical pick-up is inner position when “H”
27
FSTO
O
2/3 divider output Not used. (Open)
28
DVDD1
—
Power supply pin (+3.3 V) (digital system)
29
SFDR
O
Sled servo drive PWM signal (+) output
30
SRDR
O
Sled servo drive PWM signal (–) output
31
TFDR
O
Tracking servo drive PWM signal (+) output
32
TRDR
O
Tracking servo drive PWM signal (–) output
33
FFDR
O
Focus servo drive PWM signal (+) output
34
FRDR
O
Focus servo drive PWM signal (–) output
35
DVSS1
—
Ground pin (digital system)
36
TEST
I
Input for the test
37
TES1
I
Input for the test
38
VC
I
Middle point voltage (+1.65 V) input
39
FE
I
Focus error signal input
40
SE
I
Sled error signal input
41
TE
I
Tracking error signal input
42
CE
I
Middle point servo analog signal input
43
RFDC
I
RF signal input
44
ADIO
O
Output for the test Not used. (Open)
45
AVSS0
—
Ground pin (analog system)
46
IGEN
I
Stabilized current input for operational amplifiers
47
AVDD0
—
Power supply pin (+3.3 V) (analog system)
48
ASYO
O
EFM full-swing output
49
ASYI
I
Asymmetry comparator voltage input
50
RFAC
I
EFM signal input
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