Sony WX-7700MDX Service Manual ▷ View online
73
WX-7700MDX
Pin No.
Pin Name
I/O
Description
72
NCO
O
Not used
73
X1A
O
Sub system clock output terminal (32.768 kHz)
74
X0A
I
Sub system clock input terminal (32.768 kHz)
75
FP PULSE
I
Detection input terminal from the front panel open/close detect and open/close angle detect sensor
“L” is input when the front panel is full opened
“L” is input when the front panel is full opened
76
DSPREDY
I
Transfer enable signal input for micro controller interface from the CXD2727Q
“L”: transfer prohibition
“L”: transfer prohibition
77
MD ON
I
Power on/off signal input of the MD mechanism deck section from the MD mechanism controller
“H”: power on
“H”: power on
78
BU IN
I
Back-up power supply detect signal input from the SONY bus interface IC
“L” is input at low voltage
“L” is input at low voltage
79
KEYACK
I
Input of acknowledge detect signal for the key entry Acknowledge signal is input to accept
function and eject keys in the power off status On at input of “H”
function and eject keys in the power off status On at input of “H”
80
AD ON
O
A/D converter power control signal output terminal
When the KEYACK (pin ul) that controls reference voltage power for key A/D conversion input
is active, “L” is output from this terminal to enable the input
When the KEYACK (pin ul) that controls reference voltage power for key A/D conversion input
is active, “L” is output from this terminal to enable the input
81
ACC IN
I
Accessory power detection signal input terminal “L”: accessory power on
82
SIRCS RST
O
System reset signal output to the SIRCS controller “L”: reset
83
POWON
O
System power on/off control signal output terminal “H”: power on
84
TESTIN
I
Setting terminal for the test mode “L”: test mode, normally fixed at “H”
85
RAMBU
I
86
HSTX
I
Hardware standby signal input terminal “L”: hardware standby mode
Reset signal input in this set
Reset signal input in this set
87 to 89
MD2 to MD0
I
Setting terminal for the CPU operational mode
90
RSTX
I
System reset signal input from the reset signal generator and reset switch “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
91
VSS
—
Ground terminal
92
X0
I
Main system clock input terminal (3.8684 MHz)
93
X1
O
Main system clock output terminal (3.8684 MHz)
94
VCC
—
Power supply terminal (+5V)
95
ILLIN
I
Auto dimmer control illumination line detection signal input terminal
“L” is input at dimmer detection
“L” is input at dimmer detection
96
IDET
I
Detection signal input from the front panel open/close motor over-load detection circuit
“L”: over current
“L”: over current
97
MOT–
O
Front panel open/close motor drive signal (panel close direction) output to the BA6288FS
“H” active *2
“H” active *2
98
MOT+
O
Front panel open/close motor drive signal (panel open direction) output to the BA6288FS
“H” active *2
“H” active *2
99
CLOSE SW
I
Detection input from the front panel close detect switch “L”: front panel close
100
OPEN SW
I
Detection input from the front panel open detect switch “L”: front panel full open
101
BOOT
O
Detection signal outnput at the flash memory writing mode to the display controller
“L” is input when writing mode
“L” is input when writing mode
102 to 104
NCO
O
Not used
105
SUBP ON
O
Power on/off control signal output for the sub panel illumination LED “H”: power on
Internal RAM reset detection signal input from the RN5VD33AA
Input terminal to check that RAM data are not destroyed due to low voltage
This checking is made within 100 msec after reset
Input terminal to check that RAM data are not destroyed due to low voltage
This checking is made within 100 msec after reset
74
WX-7700MDX
*1 CD loading motor (M103) control
CD LM EJ (pin tk)
“L”
“L”
“H”
“H”
CD LM LO (pin tj)
“L”
“H”
“L”
“H”
Terminal
Operation
STOP
LODING
SAVE
BRAKE
Pin No.
Pin Name
I/O
Description
106
WAKEUP
O
Power wake up control signal output terminal for sleep release of the master controller
“H”: active
“H”: active
107 to 111
NCO
O
Not used
112
9K/10K
I
Frequency select switch input terminal
“L”: AM 10k step/FM 200k step, “H”: AM 9k step/FM 50k step
“L”: AM 10k step/FM 200k step, “H”: AM 9k step/FM 50k step
113
NCO
O
Not used
114
FSW SFT
O
control signal output for measure against AM beat to the power control IC
115
EMPH IN
I
Emphasis control signal input from the uPD63711GC and MD mechanism controller
“H”: emphasis on
“H”: emphasis on
116
PACK-IN
I
Detection input terminal from the MD disc insert detect sensor
“L”: MD disc is inserting or ejecting
“L”: MD disc is inserting or ejecting
117
FM ON
O
FM system power on/off control signal output terminal Not used
118
TUNON
O
Tuner unit power on/off control signal output “H”: tuner power on
119
VSS
—
Ground terminal
120
AMPON
O
Standby on/off control signal output to the power amplifier
“L”: standby mode, “H”: amplifier on
“L”: standby mode, “H”: amplifier on
*1 Front panel open/close motor (M640) control
MOT– (pin oj)
“L”
“L”
“H”
“H”
MOT+ (pin ok)
“L”
“H”
“L”
“H”
Terminal
Operation
STOP
FRONT PANEL
OPEN
FRONT PANEL
CLOSE
BRAKE
75
WX-7700MDX
•
MAIN BOARD IC660 RRX9000-0401R#01 (SIRCS CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
VDD
—
Power supply terminal (+3.3V)
2
VSS
—
Ground terminal
3
XIN
I
System clock input terminal (4 MHz)
4
XOUT
O
System clock output terminal (4 MHz)
5
CNVSS
—
Ground terminal
6
RESET
I
Reset signal input from the master controller “L”: reset
7, 8
F0, F1
I/O
Not used
9
G0/INT
I
SIRCS signal input from the remote control receiver
10
G1/INT
I/O
Not used
11, 12
G2, G3
I/O
Not used
13 to 16
S3 to S0
I/O
Not used
17
D3/K
O
SIRCS signal output to the master controller
18
D2/C
I/O
Not used
19, 20
D1, D0
I/O
Not used
76
WX-7700MDX
•
DISPLAY BOARD IC710 HD6432355A45F (DISPLAY CONTROLLER)
Pin No.
Pin Name
I/O
Description
1, 2
NCO
O
Not used
3
VSS
—
Ground terminal
4
NCO
O
Not used
5
VCC
—
Power supply terminal (+5V)
6 to 9
NCO
O
Not used
10
VSS
—
Ground terminal
11 to 18
NCO
O
Not used
19
VSS
—
Ground terminal
20 to 23
NCO
O
Not used
24
PEAK RST
O
Peak hold reset signal output to the peak detect IC “H”: reset
25 to 27
NCO
O
Not used
28
VSS
—
Ground terminal
29
LVL RD
I
Level reading detect signal input from the sampling timer IC
30 to 32
NCO
O
Not used
33
SP-LAT
I
Serial data latch pulse input for spectrum analyzer display from the master controller “H” active
34
BU IN
I
Back-up power supply detection signal input from the SONY bus interface
“L” is input at low voltage
“L” is input at low voltage
35, 36
VSS
—
Ground terminal
37
NCO
O
Not used
38
BUSON
I
Bus on/off control signal input (for the SONY bus) from the master controller
“L”: bus on
“L”: bus on
39
VCC
—
Power supply terminal (+5V)
40 to 43
NCO
O
Not used
44
VSS
—
Ground terminal
45 to 49
NCO
O
Not used
50
LINKOFF
O
Uni link on/off control signal output for the SONY bus interface “L”: link on, “H”: link off
51
NCO
O
Not used
52
ILLON
O
Power supply on/off control signal output of the front panel illumination LED “H”: power on
53
VSS
—
Ground terminal
54 to 56
NCO
O
Not used
57
BOOT
I
Detect signal input at the flash memory writing mode from the master controller
“L” is input when writing mode
“L” is input when writing mode
58
VCC
—
Power supply terminal (+5V)
59
NCO
O
Not used
60
LCD SO/TX
O
Display serial data output to the liquid crystal display driver IC
Output terminal for UART transfer data when writing into internal flash memory data
Output terminal for UART transfer data when writing into internal flash memory data
61
SP SI
I
Spectrum analyzer display serial data input from the CXD2727Q
62
RX
I
Input terminal for UART transfer data when writing into internal flash memory data
63
SP CLK
I
Spectrum analyzer display serial data transfer clock signal input from the master controller
64
LCD CLK
O
Display serial data transfer clock signal output to the liquid crystal display driver IC
65
VSS
—
Ground terminal
66
LCD CE0
O
Chip enable signal output to the liquid crystal display driver IC
67, 68
VSS
—
Ground terminal
69
LCD INH
O
Blank indicate control signal output to the liquid crystal display driver IC
70
LCD CE1
O
Chip enable signal output to the liquid crystal display driver IC
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