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65

Pin No.

Pin Name

I/O

Description

91

SRDR

O

Sled servo drive PWM signal (–) output to the BH6518FS

92

SFDR

O

Sled servo drive PWM signal (+) output to the BH6518FS

93

SPRD

O

Spindle servo drive PWM signal (–) output to the BH6518FS

94

SPFD

O

Spindle servo drive PWM signal (+) output to the BH6518FS

95

FGIN

I

Not used

96

TEST1

I

97

TEST2

I

98

TEST3

I

99

DVSS

—

Ground terminal (digital system)

100

EFMO

O

EFM signal output terminal when recording mode    Not used

* I (S) stands for schmitt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.

Input terminal for the test (fixed at “L”)

66

•

Pin No.

Pin Name

I/O

Description

1

I

I

I-V converted RF signal I input from the optical pick-up block detector

2

J

I

I-V converted RF signal J input from the optical pick-up block detector

3

VC

O

Middle point voltage (+1.65V) generation output terminal

4 to 9

A to F

I

Signal input from the optical pick-up detector

10

PD

I

Light amount monitor input from the optical pick-up block laser diode

11

APC

O

Laser amplifier output terminal to the automatic power control circuit

12

APCREF

I

Reference voltage input terminal for setting laser power

13

GND

—

Ground terminal

14

TEMPI

I

Connected to the temperature sensor    Not used

15

TEMPR

O

Output terminal for a temperature sensor reference voltage    Not used

16

SWDT

I

Writing serial data input from the MD mechanism controller

17

SCLK

I

Serial data transfer clock signal input from the MD mechanism controller

18

XLAT

I

Serial data latch pulse signal input from the MD mechanism controller

19

XSTBY

I

Standby signal input terminal    “L”: standby (fixed at “H” in this set)

20

F0CNT

I

Center frequency control voltage input terminal of internal circuit (BPF22, BPF3T, EQ) input
terminal

21

VREF

O

Reference voltage output terminal    Not used

22

EQADJ

I

Center frequency setting terminal for the internal circuit (EQ)

23

3TADJ

I

Center frequency setting terminal for the internal circuit (BPF3T)

24

VCC

—

Power supply terminal (+3.3V)

25

WBLADJ

I

Center frequency setting terminal for the internal circuit (BPF22)

26

TE

O

Tracking error signal output to the CXD2662R

27

CSLED

I

Connected to the external capacitor for low-pass filter of the sled error signal

28

SE

O

Sled error signal output to the CXD2662R

29

ADFM

O

FM signal output of the ADIP

30

ADIN

I

Receives a ADIP FM signal in AC coupling

31

ADAGC

I

Connected to the external capacitor for ADIP AGC

32

ADFG

O

ADIP duplex signal (22.05 kHz 

±

 1 kHz) output to the CXD2662R

33

AUX

O

Auxiliary signal (I3 signal/temperature signal) output terminal    Not used

34

FE

O

Focus error signal output to the CXD2662R

35

ABCD

O

Light amount signal (ABCD) output to the CXD2662R

36

BOTM

O

Light amount signal (RF/ABCD) bottom hold output to the CXD2662R

37

PEAK

O

Light amount signal (RF/ABCD) peak hold output to the CXD2662R

38

RF

O

Playback EFM RF signal output to the CXD2662R

39

RFAGC

I

Connected to the external capacitor for RF auto gain control circuit

40

AGCI

I

Receives a RF signal in AC coupling

41

COMPO

O

User comparator output terminal    Not used

42

COMPP

I

User comparator input terminal    Not used

43

ADDC

I

Connected to the external capacitor for cutting the low band of the ADIP amplifier

44

OPO

O

User operational amplifier output terminal    Not used

45

OPN

I

User operational amplifier inversion input terminal    Not used

46

RFO

O

RF signal output

47

MORFI

I

Receives a MO RF signal in AC coupling

48

MORFO

O

MO RF signal output

67

•

Pin No.

Pin Name

I/O

Description

1 to 5

TIN3 to TIN7

I/O

Input of the 4x8 matrix test keys (“L” is always output, except in test mode)    Not used

6

LOAD

O

MD loading motor control signal (loading direction) output to the MD mechanism deck section
motor driver    “H” active    *1

7

EJECT

O

MD loading motor control signal (eject direction) output to the MD mechanism deck section
motor driver    “H” active    *1

8, 9

NCO

O

Not used

10

MDM-ON

O

Power supply on/off control signal output of the MD mechanism deck section main power supply
and loading motor drive power supply    “H”: power on

11

E-SW

I

Inputs a MD disc loading completion detect switch detection signal
“L”: When completed of a disc loading operation

12

AG-OK

O

Output terminal of monitor in aging mode   “L”: under aging,  “H”: aging completed    Not used

13

ADJ-OK

O

Output terminal of monitor when auto adjustment completed
“L”: aging NG, “H”: aging OK    Not used

14 to 17

NCO

O

 Not used

18

DFCTSEL

I

Setting terminal for defect function
“L”: used this function , “H”: not used this function (fixed at “H” in this set)

19

DPLLSEL

I

Setting terminal for double PLL function
“L”: used this function , “H”: not used this function (fixed at “H” in this set)

20

EMPHSEL

I

Setting terminal for emphasis signal output
“L”: used this function , “H”: not used this function (fixed at “H” in this set)

21

OPEN REQ

O

Front panel open/close request signal output terminal    Not used

22

NCO

O

Not used

23

2M/4M

I

Setting terminal for D-RAM capacitance 2M bit or 4M bit    “L”: 4M bit (external D-RAM),
“H”: 2M bit (internal D-RAM of CXD2662R) (fixed at “L” in this set)

24, 25

NCO

O

Not used

26

MNT0

I

Focus OK signal input from the CXD2662R    “H” is input when focus is on (“L”: NG)

27

MNT1

I

Track jump detection signal input from the CXD2662R

28

MNT2

I

Busy monitor signal input from the CXD2662R

29

MNT3

I

Spindle servo lock status monitor signal input from the CXD2662R

30

RESET

I

System reset signal input from the master controller, reset signal generator and reset switch
“L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”

31

TX

O

Sub system clock output terminal (32.768 kHz)    Not used

32

TEX

I

Sub system clock input terminal (32.768 kHz)    Not used

33

VSS

—

Ground terminal

34

EXTAL

O

Main system clock output terminal (10 MHz)

35

XTAL

I

Main system clock input terminal (10 MHz)

36

AVSS

—

Ground terminal (for analog system)

37

AVREF

I

Reference voltage input terminal (+5V) (for A/D converter)

38

INIT

I

Initial reset signal input terminal (A/D input) (fixed at “H”)

39

TEMP

I

Temperature sensor connect terminal (A/D input)

40

ACNT

I

Setting terminal for the number of load/eject aging times (A/D input) 00h – 54h (30 times), 55h –
A9h (20 times), AAh – FFh (10 times) (fixed at “L” in this set)

41

DO-SEL

I

Setting terminal for the digital output bits (A/D input)

42

EE-CS

O

Chip select signal output to the external EEPROM device    Not used

43

EE-CKO

O

Serial data transfer clock signal output to the external EEPROM device    Not used

68

*1  Loading motor (M903) control

LOAD (pin 6)

“L”

“H”

“L”

“H”

EJECT (pin 7)

“L”

“L”

“H”

“H”

Terminal

Operation

STOP

LODING

EJECT

BRAKE

Pin No.

Pin Name

I/O

Description

44

EE-SIO

I/O

Two way data bus with the external EEPROM device    Not used

45

MD-SO

O

Writing serial data signal output to the CXD2662R and CXA2523AR

46

LINKOFF

O

Unilink on/off control signal output for the SONY bus interface    “L”: link on, “H”: link off
Not used

47

UNIREQ

O

Data request signal output terminal (for SONY bus)    “H”: request on    Not used

48

UNICKIO

I/O

Serial clock signal input from the master controller

49

UNISI

I

Serial data input from the SONY bus interface

50

UNISO

O

Serial data output to the SONY bus interface

51

MD-CKO

O

Serial data transfer clock signal output to the CXD2662R and CXA2523AR

52

MD-SI

I

Reading serial data signal input from the CXD2662R

53

NCO

O

Not used

54

SENS

I

Internal status (SENSE) input from the CXD2662R

55

CC-XINT

I

Interrupt status input from the CXD2662R

56

LIMIT-IN

I

Detection input from the MD sled limit-in detect switch
The optical pick-up is inner position when “L”

57

EJT-KEY

I

Front panel status signal input terminal    “H”: front panel full open    Not used

58

ERROR-PWM

O

PWM error monitor output terminal (C1error rate and ATER is output when test mode)
Not used

59

MD-RST

O

Reset signal output to the CXD2662R and BH6518FS    “L”: reset

60

BU-IN

I

Back-up power supply detect signal input from the SONY bus interface
“L” is input at low voltage

61

BUS-ON

I

SONY bus on/off control signal input from the master controller    “L”: bus on

62

SQSY

I

Subcode Q sync (SCOR) input from the CXD2662R
“L” is input every 13.3 msec    Almost all, “H” is input

63

C-SW

I

Inputs a MD disc loading start or a MD disc eject completion detect switch detection signal
“L”: When loading start or eject completed of a disc loading operation

64

MD-LAT

O

Serial data latch pulse signal output to the CXD2662R and CXA2523AR

65

MD-ON

O

Power supply on/off control signal output of the MD mechanism deck section main power supply
“H”: power on

66

DEEMP

O

MD emphasis control signal output to the master controller    “H”: emphasis on

67

A-ATT

O

Audio line muting on/off control signal output    “H”: muting on

68

NCO

O

Not used

69

TSTCKO

O

Output of clock signal for the test mode display    Not used

70

TSTSO

O

Output of data for the test mode display    Not used

71

TSTMOD

I

Setting terminal for the test mode    “L”: test mode, “H”: normal mode

72

VDD

—

Power supply terminal (+5V)

73

NIL

I

Not used

74 to 77

TOUT0 to TOUT3

O

In test mode, output of the 4x8 matrix test keys     Not used

78 to 80

TIN0 to TIN2

I/O

In test mode, input of the 4x8 matrix test key    In nomal mode, output “L”    Not used