Sony WX-7700MDX Service Manual ▷ View online
61
WX-7700MDX
IC504
TC74VHC157FT (EL)
IC500
CXD2727Q
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58
57
56
55
54 53 52
51
SERIAL DATA
I/F
SERIAL
DATA
I/F
MICRO
COMPUTER
I/F
512kbit
DELAY
RAM
DSP
CLOCK
GENERATOR/
TIMING CIRCUIT
DIGITAL
FILTER
CLOCK
GENERATOR/
TIMING CIRCUIT
PLL
ADC2
ADC1
–
+
+
DAC6
–
+
+
DAC5
–
+
+
DAC4
–
+
+
DAC3
–
+
+
DAC2
–
+
+
DAC1
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
PLCLK
XECKSTP
AVDP
VSS4
T. P
T. P
T. P
T. P
T. P
T. P
T. P
T. P
T. P
T. P
VDD4
AVSD
T. P
T. P
T. P
AVDD
VSS1
T. P
T. P
T. P
T. P
T. P
T. P
T. P
T. P
T. P
T. P
T. P
T. P
T. P
T. P
TST0
TST1
TST2
TST3
TST4
TST5
JPE1
JPE2
JPE3
VDD1
AVS3
AOUTL1
AVD3
AOUTR1
AVD5
AVS5
AVD1
AVS1
LREF
LIN
AVS7
AVD7
AOUTL2
AVDX
XTLO38
XTLI38
AVSX
AOUTR2
AVD8
AVS8
RIN
RREF
AVS2
AVD2
AVS6
AVD6
AOUTL3
AVD4
AOUTR3
AVS4
VSS2
XRST
BFOT
SCK
REDY
TRDT
XLAT
RVDT
XS24
VDD2
VSS3
SO1
SO2
SO3
SOUT
SI1
SI2
SI3
SIN
BCK
LRCK
XMST
VDD3
AVSP
XPLLEN
SELECT 11
1
1A
2
3
4
5
6
7
INPUT
INPUT
OUTPUT
OUTPUT
1A
1B
1Y
2A
2B
2Y
1B
1Y
2A
2B
2Y
GND 8
V
CC
STROBE
16
4A
15
14
13
11
12
11
10
INPUT
INPUT
OUTPUT
OUTPUT
G
4B
4Y
3A
4A
4B
4Y
3A
3B
9
3B
3Y
3Y
S
IC630
BA8270F-E2
1
2
3
4
5
5
6
7
8
9
10
14
13
12
11
BUS ON
SWITCH
RESET
SWITCH
BATTERY
SWITCH
BUS ON
RST
BATT
CLK
VREF
DATA
GND
VCC
RST
BUS ON
BUS ON
CLK IN
BU IN
DATA IN
DATA OUT
IC641
BA6288FS-E2
DRIVER
DRIVER
VM
4
VCC
5
FIN
6
RIN
11
NC
10
NC
9
NC
7
NC
8
VREF
12
NC
13
OUT2
14
NC
15
RNF
16
OUT1
3
NC
2
GND
1
CONTROL
LOGIC
TSD
POWER
SAVE
62
WX-7700MDX
– DISPLAY Board –
IC780
RRX9000-0601#1
IC791
TC7WH123FU (TE12R)
16
1
2
3
4
5
6
7
8
15
14
13
11 10
12
9
L IN
L IN GND
L
V STBY
VCC
NC
NC
VPO
NC
GND A
V IN
V AGC
LNS
VCO NC
GND
C
INPUT
SLAGE
320kHz
AGC
320kHz
/500kHz
PULSE
COUNTER
PULSE
FORMER
NOISE
SUPPRESSION
BANDGAP
REFERENCE
A
B
GND
VCC
RX/CX
CX
Q
CX
Q
5
6
1
2
3
4
7
8
CLR
CLR
Cx
Rx/Cx
Q
– POWER Board –
IC400, 401
TL1451ACDB-E20
REFERENCE
VOLTAGE
LATCH
TRIANGLE
OSCILLATOR
VERF.
+2.5V
+2.5V
+2.5V
+
–
U.V.L.O
–
+
+
+
–
–
1
2
3
4
5
6
7
8
9
10
16
15
14
13
12
11
PWM
COMPA-
RATOR2
RATOR2
OUTPUT2
OUTPUT1
GND
PWM
COMPA-
RATOR1
RATOR1
VERF
S
R
R
VERF
VERF
ERROR
AMP2
ERROR
AMP1
VREF/2
SHORT
CIRCUIT
PROTECTION
COMPARATOR
VCC
+
REF
OUT
S.C.P
NON-INV-
INPUT2
INV-
INPUT2
FEED
BACK2
DEAD
TIME
CONTROL2
OUT2
VCC
GND
OUT1
RT
NON-INV-
INPUT1
INV-
INPUT1
FEED
BACK1
DEAD
TIME
CONTROL1
CT
63
WX-7700MDX
5-29.
IC PIN FUNCTION DESCRIPTION
•
SERVO (MD) BOARD IC301 CXD2662R
Pin No.
Pin Name
I/O
Description
1
MNT0 (FOK)
O
Focus OK signal output to the MD mechanism controller
“H” is output when focus is on (“L”: NG)
“H” is output when focus is on (“L”: NG)
2
MNT1 (SHOCK)
O
Track jump detection signal output to the MD mechanism controller
3
MNT2 (XBUSY)
O
Busy monitor signal output to the MD mechanism controller
4
MNT3 (SLOCK)
O
Spindle servo lock status monitor signal output to the MD mechanism controller
5
SWDT
I
Writing serial data signal input from the MD mechanism controller
6
SCLK
I (S)
Serial data transfer clock signal input from the MD mechanism controller
7
XLAT
I (S)
Serial data latch pulse signal input from the MD mechanism controller
8
SRDT
O (3)
Reading serial data signal output to the MD mechanism controller
9
SENS
O (3)
Internal status (SENSE) output to the MD mechanism controller
10
XRST
I (S)
Reset signal input from the MD mechanism controller “L”: reset
11
SQSY
O
Subcode Q sync (SCOR) output to the MD mechanism controller
“L” is output every 13.3 msec Almost all, “H” is output
“L” is output every 13.3 msec Almost all, “H” is output
12
DQSY
O
Digital In U-bit CD format subcode Q sync (SCOR) output terminal
“L” is output every 13.3 msec Almost all, “H” is output Not used
“L” is output every 13.3 msec Almost all, “H” is output Not used
13
RECP
I
Laser power selection signal input terminal
“L”: playback mode, “H”: recording mode (fixed at “L” in this set)
“L”: playback mode, “H”: recording mode (fixed at “L” in this set)
14
XINT
O
Interrupt status output to the MD mechanism controller
15
TX
O
Recording data output enable signal input terminal
Writing data transmission timing input (Also serves as the magnetic head on/off output)
Not used
Writing data transmission timing input (Also serves as the magnetic head on/off output)
Not used
16
OSCI
I
System clock signal (512Fs=22.5792 MHz) input from the CXD2727Q
17
OSCO
O
System clock signal (512Fs=22.5792 MHz) output terminal Not used
18
XTSL
I
Input terminal for the system clock frequency setting
“L”: 22.5792 MHz, “H”: 45.1584 MHz (fixed at “L” in this set)
“L”: 22.5792 MHz, “H”: 45.1584 MHz (fixed at “L” in this set)
19
DIN0
I
Digital audio signal input terminal when recording mode Not used
20
DIN1
I
Digital audio signal input terminal when recording mode Not used
21
DOUT
O
Digital audio signal output terminal when playback mode Not used
22
DATAI
I
Recording data input terminal Not used
23
LRCKI
I
L/R sampling clock signal (44.1 kHz) input terminal Not used
24
XBCKI
I
Bit clock signal (2.8224 MHz) input terminal Not used
25
ADDT
I
Recording data input terminal Not used
26
DADT
O
Playback data output to the CXD2727Q
27
LRCK
O
L/R sampling clock signal (44.1 kHz) output to the CXD2727Q
28
XBCK
O
Bit clock signal (2.8224 MHz) output to the CXD2727Q
29
FS256
O
Clock signal (11.2896 MHz) output to the CXD2727Q
30
DVDD
—
Power supply terminal (+3.3V) (digital system)
31 to 34
A03 to A00
O
Address signal output to the D-RAM
35
A10
O
Address signal output to the external D-RAM Not used
36 to 40
A04 to A08
O
Address signal output to the D-RAM
41
A11
O
Address signal output to the external D-RAM Not used
42
DVSS
—
Ground terminal (digital system)
43
XOE
O
Output enable signal output to the D-RAM “L” active
44
XCAS
O
Column address strobe signal output to the D-RAM “L” active
45
A09
O
Address signal output to the D-RAM
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO SIGNAL PROCESSOR, EFM/ACIRC ENCODER/DECODER,
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER)
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER)
64
WX-7700MDX
Pin No.
Pin Name
I/O
Description
46
XRAS
O
Row address strobe signal output to the D-RAM “L” active
47
XWE
O
Write enable signal output to the D-RAM “L” active
48
D1
I/O
49
D0
I/O
50
D2
I/O
51
D3
I/O
52
MVCI
I
Digital in PLL oscillation input from the external VCO Not used
53
ASYO
O
Playback EFM full-swing output terminal
54
ASYI
I (A)
Playback EFM asymmetry comparator voltage input terminal
55
AVDD
—
Power supply terminal (+3.3V) (analog system)
56
BIAS
I (A)
Playback EFM asymmetry circuit constant current input terminal
57
RFI
I (A)
Playback EFM RF signal input from the CXA2523AR
58
AVSS
—
Ground terminal (analog system)
59
PCO
O (3)
Phase comparison output for master clock of the recording/playback EFM master PLL
60
FILI
I (A)
Filter input for master clock of the recording/playback master PLL
61
FILO
O (A)
Filter output for master clock of the recording/playback master PLL
62
CLTV
I (A)
Internal VCO control voltage input of the recording/playback master PLL
63
PEAK
I (A)
Light amount signal (RF/ABCD) peak hold input from the CXA2523AR
64
BOTM
I (A)
Light amount signal (RF/ABCD) bottom hold input from the CXA2523AR
65
ABCD
I (A)
Light amount signal (ABCD) input from the CXA2523AR
66
FE
I (A)
Focus error signal input from the CXA2523AR
67
AUX1
I (A)
Auxiliary signal (I3 signal/temperature signal) input from the CXA2523AR
68
VC
I (A)
Middle point voltage (+1.65V) input from the CXA2523AR
69
ADIO
O (A)
Monitor output of the A/D converter input signal Not used
70
AVDD
—
Power supply terminal (+3.3V) (analog system)
71
ADRT
I (A)
A/D converter operational range upper limit voltage input terminal (fixed at “H” in this set)
72
ADRB
I (A)
A/D converter operational range lower limit voltage input terminal (fixed at “L” in this set)
73
AVSS
—
Ground terminal (analog system)
74
SE
I (A)
Sled error signal input from the CXA2523AR
75
TE
I (A)
Tracking error signal input from the CXA2523AR
76
DCHG
I (A)
Connected to the +3.3V power supply
77
APC
I (A)
Error signal input for the laser automatic power control Not used
78
ADFG
I
ADIP duplex FM signal (22.05 kHz
±
1 kHz) input from the CXA2523AR
79
F0CNT
O
Filter f0 control signal output terminal Not used
80
XLRF
O
Serial data latch pulse signal output terminal Not used
81
CKRF
O
Serial data transfer clock signal output terminal Not used
82
DTRF
O
Writing serial data output terminal Not used
83
APCREF
O
Control signal output to the reference voltage generator circuit for the laser automatic power
control
control
84
LDDR
O
PWM signal output for the laser automatic power control Not used
85
TRDR
O
Tracking servo drive PWM signal (–) output to the BH6518FS
86
TFDR
O
Tracking servo drive PWM signal (+) output to the BH6518FS
87
DVDD
—
Power supply terminal (+3.3V) (digital system)
88
FFDR
O
Focus servo drive PWM signal (+) output to the BH6518FS
89
FRDR
O
Focus servo drive PWM signal (–) output to the BH6518FS
90
FS4
O
Clock signal (176.4 kHz) output terminal (X’tal system) Not used
Two-way data bus with the D-RAM (IC307)
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