Sony WX-7700MDX Service Manual ▷ View online
69
WX-7700MDX
•
MAIN BOARD IC500 CXD2727Q (DIGITAL SIGNAL PROCESSOR, DIGITAL FILTER, D/A CONVERTER)
Pin No.
Pin Name
I/O
Description
1
VSS1
—
Ground terminal (digital system)
2 to 15
T.P
I
Input terminal for the test (fixed at “L”)
16 to 21
TST0 to TST5
I
Input terminal for the test (fixed at “L”)
22 to 24
JPE1 to JPE3
I
External condition jump terminal “H”: condition jump (fixed at “L” in this set)
25
VDD1
—
Power supply terminal (+3.3V) (digital system)
26
AVS3
—
Ground terminal (for D/A converter 1) (analog system)
27
AOUTL1
O
D/A converter 1 (L-ch side) output terminal
Analog signal output for front side (L-ch side) output in this set
Analog signal output for front side (L-ch side) output in this set
28
AVD3
—
Power supply terminal (+3.3V) (for D/A converter 1) (analog system)
29
AOUTR1
O
D/A converter 1 (R-ch side) output terminal
Analog signal output for rear side (L-ch side) output in this set
Analog signal output for rear side (L-ch side) output in this set
30
AVD5
—
Power supply terminal (+3.3V) (for D/A converter 1) (analog system)
31
AVS5
—
Ground terminal (for D/A converter 1) (analog system)
32
AVD1
—
Power supply terminal (+3.3V) (for L-ch side A/D converter) (analog system)
33
AVS1
—
Ground terminal (for L-ch side A/D converter) (analog system)
34
LREF
O
Connected to the bus control for A/D converter (for L-ch side)
35
LIN
I
A/D converter (L-ch side) analog input terminal
Tuner, bus audio input signal and extarnal audio input signal (L-ch side) are input in this set
Tuner, bus audio input signal and extarnal audio input signal (L-ch side) are input in this set
36
AVS7
—
Ground terminal (for D/A converter 2) (analog system)
37
AVD7
—
Power supply terminal (+3.3V) (for D/A converter 2) (analog system)
38
AOUTL2
O
D/A converter 2 (L-ch side) output terminal Not used
39
AVDX
—
Power supply terminal (+3.3V) (for master clock) (analog system)
40
XTLO38
O
System clock output terminal (16.9344 MHz)
41
XTLI38
I
System clock input terminal (16.9344 MHz)
42
AVSX
—
Ground terminal (for master clock) (analog system)
43
AOUTR2
O
D/A converter 2 (R-ch side) output terminal
Analog signal output for sub woofer output in this set
Analog signal output for sub woofer output in this set
44
AVD8
—
Power supply terminal (+3.3V) (for D/A converter 2) (analog system)
45
AVS8
—
Ground terminal (for D/A converter 2) (analog system)
46
RIN
I
A/D converter (R-ch side) analog input terminal
Tuner, bus audio input signal and extarnal audio input signal (R-ch side) are input in this set
Tuner, bus audio input signal and extarnal audio input signal (R-ch side) are input in this set
47
RREF
O
Connected to the bus control for A/D converter (for R-ch side)
48
AVS2
—
Ground terminal (for R-ch side A/D converter) (analog system)
49
AVD2
—
Power supply terminal (+3.3V) (for R-ch side A/D converter) (analog system)
50
AVS6
—
Ground terminal (for D/A converter 3) (analog system)
51
AVD6
—
Power supply terminal (+3.3V) (for D/A converter 3) (analog system)
52
AOUTL3
O
D/A converter 3 (L-ch side) output terminal
Analog signal output for rear side (R-ch side) output in this set
Analog signal output for rear side (R-ch side) output in this set
53
AVD4
—
Power supply terminal (+3.3V) (for D/A converter 3) (analog system)
54
AOUTR3
O
D/A converter 3 (R-ch side) output terminal
Analog signal output for front side (R-ch side) output in this set
Analog signal output for front side (R-ch side) output in this set
55
AVS4
—
Ground terminal (for D/A converter 3) (analog system)
56
VSS2
—
Ground terminal (digital system)
57
XRST
I
System reset signal input from the master controller “L”: reset
58
BFOT
O
Master clock signal output terminal Used for CD master clock in this set
70
WX-7700MDX
Pin No.
Pin Name
I/O
Description
59
SCK
I
Serial data transfer clock signal input from the master controller for the micro controller interface
60
REDY
O
Transfer enable signal output for micro controller interface to the master controller
“L”: transfer prohibition
“L”: transfer prohibition
61
TRDT
O
Serial data output to the master controller and liquid crystal display controller
62
XLAT
I
Serial data latch pulse input from the master controller
63
RVDT
I
Serial data input from the master controller
64
XS24
I
Serial data 24/32 bit slot selection signal input from the master controller
“L”: 24 bit slot, “H”: 32 bit slot
“L”: 24 bit slot, “H”: 32 bit slot
65
VDD2
—
Power supply terminal (+3.3V) (digital system)
66
VSS3
—
Ground terminal (digital system)
67 to 69
SO1 to SO3
O
Serial data output terminal Not used
70
SOUT
O
Serial data output terminal Not used
71
SI1
I
CD or MD digital audio signal input terminal
72, 73
SI2, SI3
I
Serial data input terminal Not used
74
SIN
I
Serial data input terminal Not used
75
BCK
I
Serial bit transfer clock signal input terminal for CD or MD digital audio signal
76
LRCK
I
Sampling frequency clock signal input terminal for CD or MD digital audio signal
77
XMST
I
Bit clock (BCK) and L/R sampling clock (LRCK) signal master/slave mode selection signal input
from the master controller “L”: master mode, “H”: slave mode
from the master controller “L”: master mode, “H”: slave mode
78
VDD3
—
Power supply terminal (+3.3V) (digital system)
79
AVSP
—
Ground terminal (PLL system)
80
XPLLEN
I
PLL enable signal input terminal Normally: fixed at “L”
81
PLCLK
O
PLL clock signal output terminal (22.5792 MHz) for MD master clock
82
XECKSTP
I
MD PLL clock output control signal input from the master controller
At “L” is input: PLCKL (pin ia) is fixed at “L”
At “H” is input: PLCKL (pin ia) output the PLL clock signal
At “L” is input: PLCKL (pin ia) is fixed at “L”
At “H” is input: PLCKL (pin ia) output the PLL clock signal
83
AVDP
—
Power supply terminal (+3.3V) (PLL system)
84
VSS4
—
Ground terminal (digital system)
85 to 94
T.P
I
Input terminal for the test Normally: fixed at “L”
95
VDD4
—
Power supply terminal (+3.3V) (digital system)
96
AVSD
—
Ground terminal (for D-RAM)
97 to 99
T.P
I
Input terminal for the test Normally: fixed at “L”
100
AVDD
—
Power supply terminal (+3.3V) (for D-RAM)
71
WX-7700MDX
•
MAIN BOARD IC550 MB90574CPMT-G-382-BNDE1
(MASTER CONTROLLER (CD MECHANISM CONTROLLER) )
Pin No.
Pin Name
I/O
Description
1
SP LATCH
O
Serial data latch pulse output for spectrum analyzer display to the displayr controller
“H” active
“H” active
2
DSPON
O
Power on/off control signal output for the CXD2727Q power supply “H”: power on
3
DSPLAT
O
Serial data latch pulse output to the CXD2727Q
4
DSPRST
O
System reset signal output to the CXD2727Q “L”: reset
5
ATT
O
Audio line muting on/off control signal output “H”: muting on
6
SYSRST
O
System reset signal output to the MD mechanism controller, SONY bus interface IC and display
controller “L”: reset
controller “L”: reset
7
D AUDSEL
O
CD/MD selection signal output to the CD/MD selector “L”: CD, “H”: MD
Serial data 24/32 bit slot selection signal output to the CXD2727Q
“L”: 24 bit slot, “H”: 32 bit slot
Serial data 24/32 bit slot selection signal output to the CXD2727Q
“L”: 24 bit slot, “H”: 32 bit slot
8
VCC
—
Power supply terminal (+5V)
9
NCO
O
Not used
10
EE SIO
I/O
Two-way data bus with the EEPROM on the tuner unit
11
EE CKO
O
Clock signal output to the EEPROM on the tuner unit
12
RX
I
Input terminal for UART transfer data when writing into flash memory data
13
TX
O
Output terminal for UART transfer data when writing into flash memory data
14
BUSON
O
Bus on/off control signal output for SONY bus to the MD mechanism controller, SONY bus
interface IC and display controller “L”: bus on
interface IC and display controller “L”: bus on
15
BEEP
O
Beep sound drive signal output terminal “H”: beep on
16
TELMUTE
I
Telephone muting detect signal input terminal
At input of “H”, the audio signal is attenuated by 20 dB
At input of “H”, the audio signal is attenuated by 20 dB
17
UNISI
I
Serial data input from the SONY bus interface IC
18
UNISO
O
Serial data output to the SONY bus interface IC
19
UNICKO
O
Serial clock signal output for the bus interface to the MD mechanism controller, SONY bus
interface IC and display controller
interface IC and display controller
20
DSPSI
I
Serial data input from the CXD2727Q
21
DSPSO
O
Serial data output to the CXD2727Q
22
DSPCKO
O
Serial data transfer clock signal output to the CXD2727Q and display controller
23
NCO
O
Not used
24
SIRCS
I
SIRCS signal input from the SIRCS controller
25
CD SI/TSI
I
Serial data input from the uPD63711GC
26
CD SO/TSO
O
Serial data output to the uPD63711GC
27
CD CKO/TCKO
O
Serial data transfer clock signal output to the uPD63711GC
28
DSPPLL
O
MD PLL clock output control signal output to the CXD2727Q
At “L” is output: PLCKL (pin ia) is fixed at “L”
At “H” is output: PLCKL (pin ia) output the PLL clock signal
At “L” is output: PLCKL (pin ia) is fixed at “L”
At “H” is output: PLCKL (pin ia) output the PLL clock signal
29
DSPMST
O
30
NCO
O
Not used
31
VOLATT
O
Muting on/off control signal output to the TDA7402TR “L”: muting on
32
DIVER
O
Diversity selection signal output terminal Not used
Power on/off controll signal output for the CD/MD selector
“L”: power off (tuner on), “H”: power on (CD/MD on)
Bit clock (BCK) and L/R sampling clock (LRCK) signal master/slave mode selection signal
output to the CXD2727Q “L”: master mode, “H”: slave mode
“L”: power off (tuner on), “H”: power on (CD/MD on)
Bit clock (BCK) and L/R sampling clock (LRCK) signal master/slave mode selection signal
output to the CXD2727Q “L”: master mode, “H”: slave mode
72
WX-7700MDX
Pin No.
Pin Name
I/O
Description
33
VSS
—
Ground terminal
34
C
—
Connected to coupling capacitor for the power supply
35
CD XRST
O
System reset signal output to the uPD63711GC “L”: reset
36
CD A0
O
Command/parameter recognition selection signal output to the uPD63711GC
“L”: command transmission, “H”: parameter transmission
“L”: command transmission, “H”: parameter transmission
37
CD STB
O
Data strobe signal output to the uPD63711GC
38
DVCC
—
Power supply terminal (+5V) (for D/A converter)
39
DVSS
—
Ground terminal (for D/A converter)
40
FP CTRL
O
Front panel open/close motor speed control signal output to the BA6288FS
41
CD TSTB
O
CD text parameter strobe signal output to the uPD63711GC
42
AVCC
—
Power supply terminal (+5V) (for A/D converter)
43
AVRH
I
Reference voltage (+5V) input terminal (for A/D converter)
44
AVRL
I
Reference voltage (0V) input terminal (for A/D converter)
45
AVSS
—
Ground terminal (for A/D converter)
46, 47
KEYIN0,
KEYIN1
I
Key input terminal (A/D input)
48
NCO
O
Not used
49
CD ON
O
Power on/off control signal output for the CD mechanism deck section “L”: power on
50 to 52
NCO
O
Not used
53
VSM
I
S meter voltage detect signal input from the tuner unit (A/D input)
54
VCC
—
Power supply terminal (+5V)
55
CDM ON
O
Power on/off control signal output for the CD mechanism deck section “H”: power on
56
CD XTALEN
O
Not used
57
CD LM LO
O
CD loading motor control signal (loading direction) output to the BA5810FP on the CD
mechanism deck section “H” active *1
mechanism deck section “H” active *1
58
CD LM EJ
O
CD loading motor control signal (eject direction) output to the BA5810FP on the CD mechanism
deck section “H” active *1
deck section “H” active *1
59
CD RFOK
I
RFOK signal input from the uPD63711GC
60
CD PH1
I
Detection input terminal from the disc in detect sensor on the CD mechanism deck section
“L” is input when disc is loaded in
“L” is input when disc is loaded in
61
CD PH3
I
Detection input terminal from the loding completion detect sensor on the CD mechanism deck
section “L” is input after disc is loaded completely
section “L” is input after disc is loaded completely
62
CD DSW
I
Detection input terminal from the disc set detect switch on the CD mechanism deck section
“L” is input when disc is loaded and chuked
“L” is input when disc is loaded and chuked
63
VSS
—
Ground terminal
64
CD PACK
I
CD text pack synchronized signal input from the uPD63711GC
65
FSW IN
I
Oscillation frequency input for measure against AM beat
66
CD PH2
I
Detection input terminal from the CD disc size (8cm/12cm) detect sensor on the CD mechanism
deck section “L”: 8cm, “H”: 12cm
deck section “L”: 8cm, “H”: 12cm
67
CD SELFSW
I
Detection input terminal from the disc self store detect switch on the CD mechanism deck section
“L” is input when disc is loaded in
“L” is input when disc is loaded in
68
CD LIMIT
I
CD sled limit in detect switch input terminal
“L”: When the optical pick-up is inner position
“L”: When the optical pick-up is inner position
69
FLASH W
I
Detect signal Input terminal when writing into flash memory data
“L” is input when writing mode Not used
“L” is input when writing mode Not used
70
I2CSIO
I/O
IIC two-way data bus with the tuner unit and TDA7402TR
71
I2CCKO
O
IIC bus clock signal output to the tuner unit and TDA7402TR
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