Sony MDX-C8970R Service Manual ▷ View online
61
Pin No.
Pin Name
I/O
Description
107
AD-ON
O
A/D converter power control signal output terminal
When the KEYACK (pin &§ that controls reference voltage power for key A/D conversion input is
active, “L” is output from this terminal to enable the input
When the KEYACK (pin &§ that controls reference voltage power for key A/D conversion input is
active, “L” is output from this terminal to enable the input
108
NCO
O
Not used (open)
109
NOSE-SW
I
Front panel block remove/attach detection signal input terminal
“L”: front panel is attached
“L”: front panel is attached
110
CSV REQ
I
Serial data transfer request input from the CSV (IC801)
111
CSV CE
O
Chip enable signal output to the CSV (IC801) “H”: active
112
CSV RST
O
Reset signal output to the CSV (IC801) and flash memory (IC805) “L”: reset
113
NCO
O
Not used (open)
114
FM-ON
O
FM system power supply on/off control signal output
“L”: AM power on, “H”: FM power on
“L”: AM power on, “H”: FM power on
115
DOOR-SW
I
Front panel open/close detection signal input “L” is input when the front panel is closed
116
NS-MASK
O
Discharge control signal output for the noise detection circuit “H”: discharge
117
SEEK
O
Seek control signal output to the FM/AM tuner unit (TU101)
AM mode: Used for IF count output/SD output request/AGC cut at SEEK or BTM
FM mode: Used for SD speed up at SEEK, BTM, or AF
“L” is output at tuner off
AM mode: Used for IF count output/SD output request/AGC cut at SEEK or BTM
FM mode: Used for SD speed up at SEEK, BTM, or AF
“L” is output at tuner off
118
AF MUTE
O
Muting on/off control signal output for the tuner signal (FM and AM) “H”: muting on
119
VSS
—
Ground terminal
120
SSTOP
I
IF counter request signal input from the FM/AM PLL (IC151)
62
•
SERVO BOARD IC501 CXP84340-216Q (MD MECHANISM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1 to 5
TIN3 to TIN7
I/O
Input of the 4
×
8 matrix test keys (“L” is always output, except in test mode) Not used (open)
6
LOAD
O
Loading motor control signal output to the loading motor drive (IC305) “H” active *1
7
EJECT
O
Loading motor control signal output to the loading motor drive (IC305) “H” active *1
8, 9
NCO
O
Not used (open)
10
MDMON
O
Power supply on/off control signal output of the MD mechanism deck section main power supply
and loading motor drive (IC305) power supply “H”: power on
and loading motor drive (IC305) power supply “H”: power on
11
E-SW
I
Inputs the disc loading completion detect switch detection signal
“L”: When completed of the disc loading operation
“L”: When completed of the disc loading operation
12
AG-OK
O
Output of aging status in test mode “L”: under aging, “H”: aging completed Not used (open)
13
ADJ-OK
O
Output of status when aging completed in test mode “L”: aging NG, “H”: aging OK
Not used (open)
Not used (open)
14 to 17
NCO
O
Not used (open)
18
DFCTSEL
I
Select whether defect function is used for the CXD2652AR (IC301)
“L”: used this function , “H”: not used this function (fixed at “H” in this set)
“L”: used this function , “H”: not used this function (fixed at “H” in this set)
19
DPLLSEL
I
Select whether digital PLL function is used for the CXD2652AR (IC301)
“L”: used this function , “H”: not used this function (fixed at “H” in this set)
“L”: used this function , “H”: not used this function (fixed at “H” in this set)
20
EMPHSEL
I
Select whether emphasis signal output from pin or unilink data
“L”: outputs from both pin and unilink data, “H”: output from pin only (fixed at “H” in this set)
“L”: outputs from both pin and unilink data, “H”: output from pin only (fixed at “H” in this set)
21
LOCK
O
Mini-disc lock detection signal output to the liquid crystal display driver (IC701) “H”: lock
CLV lock status input in test mode
CLV lock status input in test mode
22
NCO
O
Not used (open)
23
2M/4M
I
Select whether D-RAM capacitance 2M bit or 4M bit “L”: 4M bit (external D-RAM) , “H”: 2M
bit (internal D-RAM of CXD2652AR) (fixed at “L” in this set)
bit (internal D-RAM of CXD2652AR) (fixed at “L” in this set)
24, 25
NCO
O
Not used (open)
26
MNT0
I
Focus OK signal input from the CXD2652AR (IC301)
“H” is input when focus is on (“L”: NG)
“H” is input when focus is on (“L”: NG)
27
MNT1
I
Track jump detection signal input from the CXD2652AR (IC301)
28
MNT2
I
Busy monitor signal input from the CXD2652AR (IC301)
29
MNT3
I
Spindle servo lock status monitor signal input from the CXD2652AR (IC301)
30
RESET
I
System reset signal input from the master controller (IC500), reset signal generator (IC506) and
reset switch (S703) “L”: reset For several hundreds msec. after the power supply rises, “L” is
input, then it changes to “H”
reset switch (S703) “L”: reset For several hundreds msec. after the power supply rises, “L” is
input, then it changes to “H”
31
EXTAL
O
Main system clock output terminal (10 MHz)
32
XTAL
I
Main system clock input terminal (10 MHz)
33
VSS
—
Ground terminal
34
TX
O
Sub system clock output terminal (32.768 kHz) Not used (open)
35
TEX
I
Sub system clock input terminal (32.768 kHz) Not used (fixed at “L”)
36
AVSS
—
Ground terminal (for A/D converter)
37
AVREF
I
Reference voltage input terminal (+5V) (for A/D converter)
38
INIT
I
Initial reset signal input terminal (A/D input) (fixed at “H”)
39
TEMP
I
Temperature sensor (TH501) input terminal (A/D input)
40
ACNT
I
Select the number of load/eject aging times (A/D input)
0H – 54H (30 times), 55H – OA9H (20 times), OAAH – OFFH (10 times) (fixed at “L”)
0H – 54H (30 times), 55H – OA9H (20 times), OAAH – OFFH (10 times) (fixed at “L”)
41
DO-SEL
I
Select the digital output bits (A/D input)
42
EE-CS
O
Chip select signal output to the external EEPROM device Not used (open)
43
EE-CKO
O
Serial data transfer clock signal output to the external EEPROM device Not used (open)
44
EE-SIO
I/O
Two way data bus with the external EEPROM device Not used (open)
45
MD-SO
O
Writing serial data signal output to the CXD2652AR (IC301) and CXA2523AR (IC302)
63
Pin No.
Pin Name
I/O
Description
46
LINKOFF
O
Unilink on/off control signal output for the SONY bus “L”: link on, “H”: link off
47
UNIREQ
O
Data request signal output terminal (for SONY bus) “H”: request on Not used (open)
48
UNICKIO
I/O
Serial clock signal input from the master controller (IC500) or serial clock signal output to the
SONY bus interface (IC271) and master controller (IC500) (for SONY bus)
SONY bus interface (IC271) and master controller (IC500) (for SONY bus)
49
UNISI
I
Serial data input from the SONY bus interface (IC271)
50
UNISO
O
Serial data output to the SONY bus interface (IC271)
51
MD-CKO
O
Serial data transfer clock signal output to the CXD2652AR (IC301) and CXA2523AR (IC302)
52
MD-SI
I
Reading serial data signal input from the CXD2652AR (IC301)
53
NCO
O
Not used (open)
54
SENS
I
Internal status (SENSE) input from the CXD2652AR (IC301)
55
CC-XINT
I
Interrupt status input from the CXD2652AR (IC301)
56
LIMIT-IN
I
Detection input from the sled limit-in detect switch
The optical pick-up is inner position when “L”
The optical pick-up is inner position when “L”
57
EJT-KEY
I
Eject request signal input terminal “L”: eject on Not used (fixed at “H”)
58
ERROR-PWM
O
PWM error monitor output terminal (C1and ATER is output when test mode) Not used (open)
59
MD-RST
O
Reset signal output to the CXD2652AR (IC301) and BH6511FS (IC303) “L”: reset
60
BU-IN
I
Battery detect signal input from the SONY bus interface (IC271) and battery check circuit
“H”: battery on
“H”: battery on
61
BUS-ON
I
SONY bus on/off control signal input from the master controller (IC500) “L”: bus on
62
SQSY
I
Subcode Q sync (SCOR) input from the CXD2652AR (IC301)
“L” is input every 13.3 msec Almost all, “H” is input
“L” is input every 13.3 msec Almost all, “H” is input
63
C-SW
I
Inputs the disc loading start or disc eject completion detect switch detection signal
“L”: When start or eject completed of the disc loading operation
“L”: When start or eject completed of the disc loading operation
64
MD-LAT
O
Serial data latch pulse signal output to the CXD2652AR (IC301) and CXA2523AR (IC302)
65
MD-ON
O
Power supply on/off control signal output of the MD mechanism deck section main power supply
“H”: power on
“H”: power on
66
DEEMP
O
Emphasis on/off control signal output to the master controller (IC500) “H”: emphasis on
67
A-MUTE
O
Audio muting on/off control signal output terminal
68
NCO
O
Not used (open)
69
TSTCKO
O
Output of clock signal for the test mode display Not used (open)
70
TSTSO
O
Output of data for the test mode display Not used (open)
71
TSTMOD
I
Setting terminal for the test mode “L”: test mode, “H”: normal mode
72
VCC
—
Power supply terminal (+5V)
73
NIL
I
Not used (fixed at “H”)
74 to 77
TOUT0 to TOUT3
O
Output of the 4
×
8 matrix test keys Not used (open)
78 to 80
TIN0 to TIN2
I/O
Input of the 4
×
8 matrix test keys (“L” is always output, except in test mode) Not used (open)
*1 Loading motor (M903) control
LOAD (pin 6)
“H”
“L”
“H”
“L”
EJECT (pin 7)
“L”
“H”
“H”
“L”
Terminal
Operation
IN
OUT
BRAKE
STOP
64
•
MAIN BOARD IC701 HD6432355A08F (LIQUID CRYSTAL DISPLAY DRIVE CONTROLLER)
Pin No.
Pin Name
I/O
Description
1, 2
PG3, PG4
O
Not used (open)
3
VSS
—
Ground terminal
4
NC
—
Not used (open)
5
VCC
—
Power supply terminal (+5V)
6 to 9
PC0 to PC3
O
Not used (open)
10
VSS
—
Ground terminal
11 to 14
PC4 to PC7
O
Not used (open)
15 to 18
PB0 to PB3
O
Not used (open)
19
VSS
—
Ground terminal
20 to 23
PB4 to PB7
O
Not used (open)
24 to 27
PA0 to PA3
O
Not used (open)
28
VSS
—
Ground terminal
29 to 32
PA4/IRQ4 to
PA7/IRQ7
O
Not used (open)
33
SP-LAT
I
Serial data latch pulse input for spectrum display from the master controller (IC500)
“H” active
“H” active
34
P66/IRQ2
O
Not used (open)
35, 36
VSS
—
Ground terminal
37
P65/IRQ1
O
Not used (open)
38
BUS-ON
I
Bus on/off control signal output from the master controller (IC500)
“L”: bus on
“L”: bus on
39
VCC
—
Power supply terminal (+5V)
40
CD/MD
I
Setting terminal for the internal mechanism CD or MD
“L”: CD, “H”: MD (fixed at “H” in this set)
“L”: CD, “H”: MD (fixed at “H” in this set)
41 to 43
PE1 to PE3
O
Not used (open)
44
VSS
—
Ground terminal
45
TIR IND
O
LED drive signal output of the TIR indicator (LED705) “H”: LED on
46, 47
PE5, PE6
O
Not used (open)
48
MD LOCK
I
Mini-disc lock detection signal input from the MD mechanism controller (IC501)
“H”: lock CLV lock status output in test mode
“H”: lock CLV lock status output in test mode
49
BU-IN
I
Battery detect signal input from the SONY bus interface (IC271) and battery detect circuit
“L” is input at low voltage
“L” is input at low voltage
50
LINK-OFF
O
Link on/off control signal output for the SONY bus “L”: link on, “H”: link off
Not used (open)
Not used (open)
51
PD2
O
Not used (open)
52
ILL-ON
O
Power on/off control signal output of the illumination LED “H”: power on
53
VSS
—
Ground terminal
54
DOOR-SW
I
Front panel open/close detection signal input “L” is input when the front panel is closed
55
NCO
O
Not used (open)
56
PD6
O
Not used (open)
57
BOOT
I
Serial data input at the flash memory writing mode “L” is input when writing change
58
VCC
—
Power supply terminal (+5V)
59
NCO
O
Not used (open)
60
TX/FL-SO/
LCDDATA
O
Display serial data output to the liquid crystal display driver (IC900, 920)
Output terminal for UART transfer data when writing into internal flash memory data
Output terminal for UART transfer data when writing into internal flash memory data
61
SP-SI
I
Spectrum analyzer display serial data input from the CXD2727Q (IC300)
62
RX
I
Input terminal for UART transfer data when writing into internal flash memory data
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