Sony MDX-C8970R Service Manual ▷ View online
49
IC952
MSM6685JSDR1
1
2
3
4
42
41
40
39
38
37
36
32
31
30
29
35
34
33
5
6
7
8
9
10
12
13
14
11
15
16
17 18
19 20 21 22 23 24
25
26
27
28
43
44
45
47
48
49
50
52
53
54
55
56
51
46
MCU I/F
STATUS
REGISTER
TEST
CIRCUIT
12BIT
ADC
LPF
12BIT
DAC
+
-
+
-
SG
CIRCUIT
ADDRESS
CONTROLLER
ADPCM
ANALYZER/
SYNTHESIZER
TIMING
CONTROLLER
OSC
DATA
I/O
REGISTER
CONTROLLER
D0
D1
D2
D3
BUSY
RPM
VPM
TEST
TEST
TEST
TEST
TEST
MCUM
CE
ACON
CS3
CS2
CS1
SADX
SADY
SADY
PDWN
TEST
TEST
AGND
RSEL2
RSEL1
RSEL1
DGND
TEST
TEST
ADIN
FOUT
AOUT
FIN
AMON
DVDD
AVDD
SG
SGC
LOUT
LINE
MOUT
MIN
CE
WR
RD
RESET
NAR
RWCK
DVDD
XT
XT
WE
DROM
DI/0
CS4
TAS
SAS
MON
TIMING
GENERATOR
8,388,608DATA
REGISTER
COLUMN DECODER
COLUMN ADDRESS
COUNTER
ROW
DECODER
ADDRESS
MULTIPLEXER
REFRESH ADDRESS
COUNTER
ROW ADDRESS
COUNTER
ROW ADDRESS
REGISTER
REFRESH TIMER
I/O CONTROL
WRITE CLOCK
GENERATOR
2
3
4
5
11
12
13
10
9
1
25
24
23
22
18
17
16
15
14
26
TEST
RWCK
NC
TEST
TEST
TEST
TEST
TEST
DIN
NC
VSS
VCC
RS/A
RFSH
SAD
SAS
TAS
CS
WE
DOUT
NC
IC951
MSM6688GS-2K
50
IC803
MSM534001E-49TSKFDR3 (TYPE C)
MSM534001E-50TSKFDR3 (TYPE A)
MSM534001E-51TSKFDR3 (TYPE B)
MSM534001E-51TSKFDR3 (TYPE B)
1
57
58
59
60
61
62
63
64
49
50
51
52
53
55
56
6
2 3
5
4
EXTERNAL MEMORY
INTERFACE
ADC
MUX
DATA BUS
8
7
9
14
10 11
13
12
16
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
19
18
17
15
A15
A14
A13
A12
A11
A10
A9
A8
GND
VDD
A7
A6
A5
A4
A3
A2
A0
A1
P10
P11
P12
P13
P14
P15
P16
P17
VDD
GND
RESET
XI1
P07
DACOUT
XO1
D7
D6
D5
D4
D3
D2
D1
D0
AIN1
AIN0
AGND
BUFOUT/PWM0
TEST/PWM1
AVDD
GND
SH
PORT 1
ADDRESS BUS
INTERNAL BUS
REGISTER
SPACE
STACK
SPACE
SPACE
CPU
PORT 0
PULSE WIDTH
MODULATOR
TIMER
OSC
INTERNAL ROM
32 X 8 (HIGH)
INTERNAL ROM
32 X 8 (LOW)
WAKEUP LOGIC
(FROM PORT 0/1)
BUFFER
SLEEP
PON
WRD
RDD
WRC
RDC
GND
VDD
P00
P01
P02
P03
P04
P05
P06
XML
XMH
INTERRUPT
LOGIC
DAC
ADC
ADC
ANALOG
CONTROL
54
POWER
CONTROL
TIMING &
CONTROL
CONTROL
1
6
2 3
5
4
CE/OE
CONTROL
MEMORY CELL
MATRIX
524,288 X 8
X
DECODER
ADDRESS
BUFFER
Y
DECODER
MULTIPLEXER
OUTPUT
BUFFER
OE
A10
CE
D7
D6
D5
D4
D3
VSS
D2
D1
D0
A0
A1
A2
A3
8
7
9
14
10 11
13
12
16
15
32
27
31 30
28
29
25
26
24
19
23 22
20
21
17
18
A11
A9
A8
A13
A14
A17
A18
VCC
NC
A16
A15
A12
A7
A6
A5
A4
– POWER Board –
IC801
RSC-164
51
IC805
MBM29F800TA
IC871
TL1451ACDB-E20
CONTROL
CIRCUIT
LOW VCC
DETECTOR CIRCUIT
WRITE/ERASE
PULSE TIMER
PULSE TIMER
ERASE CIRCUIT
RY/BY
BUFFER
CHIP ENABLE/
OUTPUT ENABLE
CIRCUIT
I/O
BUFFER
DATA
LATCH
ADDRESS
LATCH
Y
DECODER
8,388,608
CELL
MATRIX
Y GATE
WRITE CIRCUIT
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
DQ3
DQ11
VCC
DQ4
DQ12
DQ5
DQ13
DQ7
DQ14
DQ6
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
GND
CE
OE
1
2
3
4
4
5
6
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
21
22
A8
A9
A15
A14
A13
A13
A12
A11
NC
RY/BY
WE
A7
A6
A6
A4
A5
NC
NC
RESET
NC
47
48
45
46
A3
A2
A2
A1
A17
A10
X
DECODER
A16
BYTE
GND
DQ15/A–1
A0
STB
STB
A18
REFERENCE
VOLTAGE
LATCH
TRIANGLE
OSCILLATOR
VERF.
+2.5V
+2.5V
+2.5V
+
–
U.V.L.O
–
+
+
+
–
–
1
2
3
4
5
6
7
8
9
10
16
15
14
13
12
11
PWM
COMPA-
RATOR2
RATOR2
OUTPUT2
OUTPUT1
GND
PWM
COMPA-
RATOR1
RATOR1
VERF
S
R
R
VERF
VERF
ERROR
AMP2
ERROR
AMP1
VREF/2
SHORT
CIRCUIT
PROTECTION
COMPARATOR
VCC
+
REF
OUT
S.C.P
NON-INV-
INPUT2
INV-
INPUT2
FEED
BACK2
DEAD
TIME
CONTROL2
OUT2
VCC
GND
OUT1
RT
NON-INV-
INPUT1
INV-
INPUT1
FEED
BACK1
DEAD
TIME
CONTROL1
CT
52
5-23.
IC PIN FUNCTION DESCRIPTION
•
MAIN BOARD IC300 CXD2727Q (DIGITAL SIGNAL PROCESSOR, DIGITAL FILTER, D/A CONVERTER)
Pin No.
Pin Name
I/O
Description
1
VSS1
—
Ground terminal (digital system)
2 to 15
T.P
I
Input terminal for the test (fixed at “L”)
16 to 21
TST0 to TST5
I
Input terminal for the test (fixed at “L”)
22 to 24
JPE1 to JPE3
I
External condition jump terminal “H”: condition jump (fixed at “L”)
25
VDD1
—
Power supply terminal (+3.3V) (digital system)
26
AVS3
—
Ground terminal (for D/A converter 1) (analog system)
27
AOUTL1
O
D/A converter 1 (L-ch side) output terminal
Analog signal output for front side (L-ch side) output in this set
Analog signal output for front side (L-ch side) output in this set
28
AVD3
—
Power supply terminal (+3.3V) (for D/A converter 1) (analog system)
29
AOUTR1
O
D/A converter 1 (R-ch side) output terminal
Analog signal output for rear side (L-ch side) output in this set
Analog signal output for rear side (L-ch side) output in this set
30
AVD5
—
Power supply terminal (+3.3V) (for D/A converter 1) (analog system)
31
AVS5
—
Ground terminal (for D/A converter 1) (analog system)
32
AVD1
—
Power supply terminal (+3.3V) (for L-ch side A/D converter) (analog system)
33
AVS1
—
Ground terminal (for L-ch side A/D converter) (analog system)
34
LREF
O
Connected to the bus control for A/D converter (for L-ch side)
35
LIN
I
A/D converter (L-ch side) analog input terminal
Tuner and bus audio input signal (L-ch side) in this set
Tuner and bus audio input signal (L-ch side) in this set
36
AVS7
—
Ground terminal (for D/A converter 2) (analog system)
37
AVD7
—
Power supply terminal (+3.3V) (for D/A converter 2) (analog system)
38
AOUTL2
O
D/A converter 2 (L-ch side) output terminal Not used (open)
39
AVDX
—
Power supply terminal (+3.3V) (for master clock) (analog system)
40
XTLO38
O
System clock output terminal (16.9344 MHz)
41
XTLI38
I
System clock input terminal (16.9344 MHz)
42
AVSX
—
Ground terminal (for master clock) (analog system)
43
AOUTR2
O
D/A converter 2 (R-ch side) output terminal
Analog signal output for sub woofer output in this set
Analog signal output for sub woofer output in this set
44
AVD8
—
Power supply terminal (+3.3V) (for D/A converter 2) (analog system)
45
AVS8
—
Ground terminal (for D/A converter 2) (analog system)
46
RIN
I
A/D converter (R-ch side) analog input terminal
Tuner and bus audio input signal (R-ch side) in this set
Tuner and bus audio input signal (R-ch side) in this set
47
RREF
O
Connected to the bus control for A/D converter (for R-ch side)
48
AVS2
—
Ground terminal (for R-ch side A/D converter) (analog system)
49
AVD2
—
Power supply terminal (+3.3V) (for R-ch side A/D converter) (analog system)
50
AVS6
—
Ground terminal (for D/A converter 3) (analog system)
51
AVD6
—
Power supply terminal (+3.3V) (for D/A converter 3) (analog system)
52
AOUTL3
O
D/A converter 3 (L-ch side) output terminal
Analog signal output for rear side (R-ch side) output in this set
Analog signal output for rear side (R-ch side) output in this set
53
AVD4
—
Power supply terminal (+3.3V) (for D/A converter 3) (analog system)
54
AOUTR3
O
D/A converter 3 (R-ch side) output terminal
Analog signal output for front side (R-ch side) output in this set
Analog signal output for front side (R-ch side) output in this set
55
AVS4
—
Ground terminal (for D/A converter 3) (analog system)
56
VSS2
—
Ground terminal (digital system)
57
XRST
I
System reset signal input from the master controller (IC500) “L”: reset
58
BFOT
O
Master clock signal output terminal Not used (open)
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