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57

•

Pin No.

Pin Name

I/O

Description

1

I

I

I-V converted RF signal I input from the optical pick-up block detector

2

J

I

I-V converted RF signal J input from the optical pick-up block detector

3

VC

O

Middle point voltage (+1.65V) generation output terminal

4 to 9

A to F

I

Signal input from the optical pick-up detector

10

PD

I

Light amount monitor input from the optical pick-up block laser diode

11

APC

O

Laser amplifier output terminal to the automatic power control circuit

12

APCREF

I

Reference voltage input terminal for setting laser power from the CXD2652AR (IC301)

13

GND

—

Ground terminal

14

TEMPI

I

Connected to the temperature sensor    Not used (open)

15

TEMPR

O

Output terminal for a temperature sensor reference voltage    Not used (open)

16

SWDT

I

Writing serial data input from the MD mechanism controller (IC501)

17

SCLK

I

Serial data transfer clock signal input from the MD mechanism controller (IC501)

18

XLAT

I

Serial data latch pulse signal input from the MD mechanism controller (IC501)

19

XSTBY

I

Standby signal input terminal    “L”: standby (fixed at “H” in this set)

20

F0CNT

I

Center frequency control voltage input terminal of internal circuit (BPF22, BPF3T, EQ) input 
terminal

21

VREF

O

Reference voltage output terminal    Not used (open)

22

EQADJ

I

Center frequency setting terminal for the internal circuit (EQ)

23

3TADJ

I

Center frequency setting terminal for the internal circuit (BPF3T)

24

VCC

—

Power supply terminal (+3.3V)

25

WBLADJ

I

Center frequency setting terminal for the internal circuit (BPF22)

26

TE

O

Tracking error signal output to the CXD2652AR (IC301)

27

CSLED

I

Connected to the external capacitor for low-pass filter of the sled error signal

28

SE

O

Sled error signal output to the CXD2652AR (IC301)

29

ADFM

O

FM signal output of the ADIP

30

ADIN

I

Receives a ADIP FM signal in AC coupling

31

ADAGC

I

Connected to the external capacitor for ADIP AGC

32

ADFG

O

ADIP duplex signal (22.05 kHz 

±

 1 kHz) output to the CXD2652AR (IC301)

33

AUX

O

Auxiliary signal (I

3

 signal/temperature signal) output terminal    Not used (open)

34

FE

O

Focus error signal output to the CXD2652AR (IC301)

35

ABCD

O

Light amount signal (ABCD) output to the CXD2652AR (IC301)

36

BOTM

O

Light amount signal (RF/ABCD) bottom hold output to the CXD2652AR (IC301)

37

PEAK

O

Light amount signal (RF/ABCD) peak hold output to the CXD2652AR (IC301)

38

RF

O

Playback EFM RF signal output to the CXD2652AR (IC301)

39

RFAGC

I

Connected to the external capacitor for RF auto gain control circuit

40

AGCI

I

Receives a RF signal in AC coupling

41

COMPO

O

User comparator output terminal    Not used (open)

42

COMPP

I

User comparator input terminal    Not used (fixed at “L”)

43

ADDC

I

Connected to the external capacitor for cutting the low band of the ADIP amplifier

44

OPO

O

User operational amplifier output terminal    Not used (open)

45

OPN

I

User operational amplifier inversion input terminal    Not used (fixed at “L”)

46

RFO

O

RF signal output terminal

47

MORFI

I

Receives a MO RF signal in AC coupling

48

MORFO

O

MO RF signal output terminal

58

• 

Pin No.

Pin Name

I/O

Description

1

RE-IN0

I

2

RE-IN1

I

3

TIR-BUSY

I

Busy detection signal input from the MSM6688GS-2K (IC951)
“H” is output while MSM6688GS-2K (IC951) is executing a command

4

TIR-PDOWN

O

Power down control signal output to the MSM6688GS-2K (IC951)    “L”: power down

5

TIR-RST

O

Reset signal output to the MSM6688GS-2K (IC951)    “H”: reset

6

SYSRST

O

System reset signal output to the MD mechanism controller (IC501),  SONY bus interface 
(IC271) and liquid crystal display drive controller (IC701)    “L”: reset

7

BUS- ON

O

Bus on/off control signal output to the MD mechanism controller (IC501),  SONY bus interface 
(IC271) and liquid crystal display drive controller (IC701)    “L”: bus on

8

VCC

—

Power supply terminal (+5V)

9

DSP STP

O

PLL clock output control signal to the CXD2727Q (IC300)
At “L” is output: fixed at “L” is PLCLK (pin *¡ of IC300 CXD2727Q) 
At “H” is output: PLL clock signal output from the PLCLK (pin *¡ of IC300 CXD2727Q)

10

NCO

O

Not used (open)

11

CSV PLAY

O

Voice guide and DSP sound selection to the CSV mix switch (IC691)    “L”: voice guide mode

12

FLS SI

I

Input terminal at the flash memory data write mode

13

FLS SO

O

Output terminal at the flash memory data write mode

14

FLASH-W

I

Internal flash memory data write mode detection signal input terminal    “L”: data write mode
Not used (fixed at “H” in this set)

15

BEEP

O

Beep sound drive signal output terminal

16

CSV ON

O

CSV (IC801) power supply control output terminal    “H”: CSV power on

17

DSP SI

I

Serial data input from the CXD2727Q (IC300)

18

DSP SO

O

Serial data output to the CXD2727Q (IC300)

19

DSP CLK

O

Serial data transfer clock signal output to the CXD2727Q (IC300) and liquid crystal display drive 
controller (IC701)

20

UNI SI

I

Serial data input from the SONY bus interface (IC271)

21

UNI SO

O

Serial data output to the SONY bus interface (IC271)

22

UNI CKIO

I/O

Serial clock signal output to the MD mechanism controller (IC501), SONY bus interface (IC271) 
and liquid crystal display drive controller (IC701) or serial clock signal input from the MD 
mechanism controller (IC501) (for SONY bus)

23

SD-IN

I

Station detector detect input from the FM/AM tuner unit (TU101)
Stop level for SEEK, BTM, etc. is determined    SD is present at input of “H”

24

SIRCS

I

Sircs remote control signal input from the remote control receiver (IC910)

25

CSV-SI

I

Serial data input from the CSV (IC801)

26

CSV-SO

O

Serial data output to the CSV (IC801)

27

CSV-CKO

O

Serial data transfer clock signal output to the CSV (IC801)

28

DSP RST

O

Reset signal output to the CXD2727Q (IC300)    “L”: reset

29

ST-MONO

I/O

FM stereo broadcasting detection signal input from the FM/AM tuner unit (TU101), or forced 
monaural control signal output to the FM/AM tuner unit (TU101)
“L” is input in the FM stereo mode, or “L” is output in the forced monaural mode

30

DSP XMST

O

Bit clock (BCK) and L/R sampling clock (LRCK) signal master/slave mode selection signal 
output to the CXD2727Q (IC300)
“L”: master mode, “H”: slave mode

31

WIDE

O

Jog dial pulse input of the rotary encoder (EN900)
 (for VOLUME/BASS/TREBLE/BALANCE/FADER control)

IF band select signal output terminal    “H”: wide mode
In receiving FM signals, interference noise from adjacent stations is removed by narrowing the 
IF band automatically in the tuner unit so as to raise the selectivity, but in this case, the distortion 
may increase and accordingly, the IF band is widened forcibly

59

Pin No.

Pin Name

I/O

Description

32

NARROW

O

33

VSS

—

Ground terminal

34

C

—

Connected to coupling capacitor for the power supply

35

RAMBU

I

Internal RAM reset detection signal input terminal
Input terminal to check that RAM data are not destroyed due to low voltage
This checking is made within 100 msec after reset    Not used (open)

36

MUTE

O

Audio line muting on/off control signal output terminal    “H”: muting on

37

AUDIO SEL0

O

Analog signal source selection output to the CXD2727Q (IC300)

38

DVCC

—

Power supply terminal (+5V) (for D/A converter)

39

DVSS

—

Ground terminal (for D/A converter)

40

AUDIO SEL1

O

Analog signal source selection output to the CXD2727Q (IC300)

41

LCDANG

O

View field angle control signal is output when front panel is fully opened
“H”: front panel is fully opened

42

AVCC

—

Power supply terminal (+5V) (for A/D converter)

43

AVRH

I

Reference voltage (+5V) input terminal (for A/D converter)

44

AVRL

I

Reference voltage (0V) input terminal (for A/D converter)

45

AVSS

—

Ground terminal (for A/D converter)

46

VSM

(S-METER)

I

FM and AM signal meter voltage detection input from the FM/AM tuner unit (TU101)
(A/D input)

47

KEY-IN0

I

Key input terminal (A/D input) (LSW900, S900, LSW901 to LSW904, LSW906)
OFF, SEEK/AMS 

+ ) +  = 0 – , SOURCE, SHIFT, MODE, SOUND, DSPL keys 

input

48

KEY-IN1

I

Key input terminal (A/D input) (LSW902, LSW905, LSW907 to LSW918)
6, LIST, PTY, AF/TA, TIR, 10 to 3 keys input

49

RC-IN0

I

Rotary remote commander key input terminal (A/D input)

50

DSTSEL0

I

Destination setting terminal (fixed at “L”)

51

DSTSEL1

I

Destination setting terminal (fixed at “H”)

52

QUALITY

I

Noise level detection signal input at SEEK mode

53

MTP

I

Multi-path detection signal input from the RDS decoder (IC901)

54

VCC

—

Power supply terminal (+5V)

55

VOL LOAD

O

Serial data latch pulse output to the electrical volume (IC602, IC632)

56

VOL DATA L

O

Setting data output (L-ch) to the electrical volume (IC602)

57

VOL DATA R

O

Setting data output (R-ch) to the electrical volume (IC632)

58

VOL CLK

O

Serial clock signal output to the electrical volume (IC602, IC632)

59

DSP XLAT

O

Serial data latch pulse signal output to the CXD2727Q (IC300)

60

RC-IN1

I

Rotary remote commander shift key input terminal    “L”: shift

61

ACC IN

I

Accessory detect signal input terminal    “L”: accessory on

62

POW-ON

O

Main system power supply on/off control signal output    “H”: power on

63

VSS

—

Ground terminal

64

BOOT

O

Serial data output to the liquid crystal display drive controller (IC701)
“L” is output when writing change

65

PWM IN

I

Power supply control signal input from the power control (IC871)

66

NCO

O

Not used (open)

67

RDS-DAVN

I

Data transmit completed detect signal input from the RDS decoder (IC901)   “H”: active

68

CD/MD

I

Setting for the internal mechanism CD or MD
“L”: CD, “H”: MD (fixed at “H” in this set)

IF band select signal output to the FM/AM tuner unit (TU101)    “H”: narrow mode
In receiving FM signals, interference noise from adjacent stations is removed by narrowing the 
IF band automatically in the tuner unit so as to raise the selectivity

60

Pin No.

Pin Name

I/O

Description

69

CD/MD ON

I

CD/MD servo power supply input detect terminal

70

I2C-SDA

I/O

Two-way data bus with the FM/AM PLL (IC151)

71

I2C-SCL

O

Serial clock signal output to the FM/AM PLL (IC151)

72

SHIFT OUT

O

Shift clock control signal output of the power control (IC871)

73

X1A

O

Sub system clock output terminal (32.768 kHz)

74

X0A

I

Sub system clock input terminal (32.768 kHz)

75

NCO

O

Not used (open)

76

KEYACK

I

Input of acknowledge signal for the key entry    Acknowledge signal is input to accept function
and eject keys in the power off status    On at input of “H”

77

BU-IN

I

Battery detect signal input from the SONY bus interface (IC271) and battery detect circuit
“L” is input at low voltage

78

SP LATCH

O

Serial data latch pulse output for spectrum analyzer section to the liquid display drive controller
(IC701)

79

DSP REDY

I

Transfer enable signal output from the liquid crystal display drive controller (IC701)
“L”: transfer prohibition, “H”: transfer permission

80

TEST

I

Setting terminal for the test mode    “L”: test mode, Normally: fixed at “H”

81

EMPH

O

Emphasis control signal output to the MD mechanism controller (IC501)

82

WAKE UP

O

DC/DC converter power supply on/off control signal output terminal   Not used (open)

83

TEL-MUTE

I

Telephone muting signal input terminal    At input of “L”, the signal is attenuated by –20 dB

84

TU-ON

O

Tuner system power supply on/off control signal output    “H”: tuner power on

85

ILL IN

I

Auto dimmer control illumination line detection signal input terminal
“L” is input at dimmer detection

86

HSTX

I

Hardware standby input terminal    “L”: hardware standby mode    Reset signal input in this set

87

MD2

I

Setting terminal for the CPU operational mode (fixed at “L” in this set)

88

MD0

I

Setting terminal for the CPU operational mode (fixed at “H” in this set)

89

MD1

I

Setting terminal for the CPU operational mode (fixed at “H” in this set)

90

RESET

I

System reset signal input from the reset signal generator (IC506) and reset switch (S703)
“L”: reset    “L” is input for several 100 msec after power on, then it changes to “H”

91

VSS

—

Ground terminal

92

X0

I

Main system clock input terminal (3.58 MHz)

93

X1

O

Main system clock output terminal (3.58 MHz)

94

VCC

—

Power supply terminal (+5V)

95

DOOR-IND

O

LED drive signal output of the illumination LED (LED706)   “H”: LED on
“H” is output to turn on LED when front panel is opened

96

DSP ON

O

Power supply on/off control signal output for the CXD2727Q (IC300)    “H”: DSP on

97

NCO

O

Not used (open)

98

AMP STBY

O

Standby on/off control signal output to the power amplifier (IC481)
“L”: standby mode, “H”: amp on

99 to 102

TIR-D0 to

TIR-D3

I/O

Two-way data bus with the MSM6688GS (IC951)

103

TIR-RD

O

Data read strobe signal output to the MSM6688GS (IC951)
“L” is output when data (D0 to D3) are output to the MSM6688GS (IC951)

104

TIR-WR

O

Data write strobe signal output to the MSM6688GS (IC951)
“L” is output when data (D0 to D3) are output to the MSM6688GS (IC951)

105

TIR-CE1

O

106

TIR-CE0

O

Chip enable signal output to the MSM6688GS (IC951)
TIR-WR (pin !‚› or TIR-RD (pin !‚‹ is accepted when CE1 is “L” or CE0 is “H” respectively
TIR-WR (pin !‚› or TIR-RD (pin !‚‹ is not accepted when CE1 is “H” or CE0 is “L” respectively