Sony MDX-C8970R Service Manual ▷ View online
53
Pin No.
Pin Name
I/O
Description
59
SCK
I
Serial data transfer clock signal input from the master controller (IC500) and liquid crystal display
drive controller (IC701)
drive controller (IC701)
60
REDY
O
Transfer enable signal output to the master controller (IC500)
“L”: transfer prohibition
“L”: transfer prohibition
61
TRDT
O
Serial data output to the master controller (IC500) and liquid crystal display drive controller
(IC701)
(IC701)
62
XLAT
I
Serial data latch pulse input from the master controller (IC500)
63
RVDT
I
Serial data input from the master controller (IC500)
64
XS24
I
Serial data 24/32 bit slot selection signal input terminal
“L”: 24 bit slot, “H”: 32 bit slot (validity at slave mode) (fixed at “H” in this set)
“L”: 24 bit slot, “H”: 32 bit slot (validity at slave mode) (fixed at “H” in this set)
65
VDD2
—
Power supply terminal (+3.3V) (digital system)
66
VSS3
—
Ground terminal (digital system)
67 to 69
SO1 to SO3
O
Serial data output terminal Not used (open)
70
SOUT
O
Serial data output terminal Not used (open)
71
SI1
I
Serial data input from the CXD2652AR (IC301)
72, 73
SI2, SI3
I
Serial data input terminal Not used (open)
74
SIN
I
Serial data input terminal Not used (open)
75
BCK
I
Bit clock signal (2.8224 MHz) input from the CXD2652AR (IC301)
76
LRCK
I
L/R sampling clock signal (44.1 kHz) input from the CXD2652AR (IC301)
77
XMST
I
Bit clock (BCK) and L/R sampling clock (LRCK) signal master/slave mode selection signal input
from the master controller (IC500) “L”: master mode, “H”: slave mode
from the master controller (IC500) “L”: master mode, “H”: slave mode
78
VDD3
—
Power supply terminal (+3.3V) (digital system)
79
AVSP
—
Ground terminal (PLL system)
80
XPLLEN
I
PLL enable signal input terminal Normally: fixed at “L”
81
PLCLK
O
PLL clock signal output terminal (22.5792 MHz)
82
XECKSTP
I
PLL clock output control signal input from the master controller (IC500)
At “L” is input: fixed at “L” is PLCLK (pin *¡)
At “H” is input: PLL clock signal output from the PLCLK (pin *¡)
At “L” is input: fixed at “L” is PLCLK (pin *¡)
At “H” is input: PLL clock signal output from the PLCLK (pin *¡)
83
AVDP
—
Power supply terminal (+3.3V) (PLL system)
84
VSS4
—
Ground terminal (digital system)
85 to 94
T.P
I
Input terminal for the test Normally: fixed at “L”
95
VDD4
—
Power supply terminal (+3.3V) (digital system)
96
AVSD
—
Ground terminal (for D-RAM)
97 to 99
T.P
I
Input terminal for the test Normally: fixed at “L”
100
AVDD
—
Power supply terminal (+3.3V) (for D-RAM)
54
•
SERVO BOARD IC301 CXD2652AR
Pin No.
Pin Name
I/O
Description
1
MNT0
O
Focus OK signal output to the MD mechanism controller (IC501)
“H” is output when focus is on (“L”: NG)
“H” is output when focus is on (“L”: NG)
2
MNT1
O
Track jump detection signal output to the MD mechanism controller (IC501)
3
MNT2
O
Busy monitor signal output to the MD mechanism controller (IC501)
4
MNT3
O
Spindle servo lock status monitor signal output to the MD mechanism controller (IC501)
5
SWDT
I
Writing serial data signal input from the MD mechanism controller (IC501)
6
SCLK
I
Serial data transfer clock signal input from the MD mechanism controller (IC501)
7
XLAT
I
Serial data latch pulse signal input from the MD mechanism controller (IC501)
8
SRDT
O (3)
Reading serial data signal output to the MD mechanism controller (IC501)
9
SENS
O (3)
Internal status (SENSE) output to the MD mechanism controller (IC501)
10
XRST
I
Reset signal input from the MD mechanism controller (IC501) “L”: reset
11
SQSY
O
Subcode Q sync (SCOR) output to the MD mechanism controller (IC501)
“L” is output every 13.3 msec Almost all, “H” is output
“L” is output every 13.3 msec Almost all, “H” is output
12
DQSY
O
Digital In U-bit CD format subcode Q sync (SCOR) output terminal
“L” is output every 13.3 msec Almost all, “H” is output Not used (open)
“L” is output every 13.3 msec Almost all, “H” is output Not used (open)
13
RECP
I
Laser power selection signal input terminal
“L”: playback mode, “H”: recording mode (fixed at “L” in this set)
“L”: playback mode, “H”: recording mode (fixed at “L” in this set)
14
XINT
O
Interrupt status output to the MD mechanism controller (IC501)
15
TX
I
Recording data output enable signal input terminal
Writing data transmission timing input (Also serves as the magnetic head on/off output)
Not used (fixed at “L”)
Writing data transmission timing input (Also serves as the magnetic head on/off output)
Not used (fixed at “L”)
16
OSCI
I
System clock signal (512Fs=22.5792 MHz) input from the CXD2727Q (IC300)
17
OSCO
O
System clock signal (512Fs=22.5792 MHz) output terminal Not used (open)
18
XTSL
I
Input terminal for the system clock frequency setting
“L”: 45.1584 MHz, “H”: 22.5792 MHz (fixed at “H” in this set)
“L”: 45.1584 MHz, “H”: 22.5792 MHz (fixed at “H” in this set)
19
RVDD
—
Power supply terminal (+3.3V) (digital system)
20
RVSS
—
Ground terminal (digital system)
21
DIN
I
Digital audio signal input terminal when recording mode Not used (fixed at “L”)
22
DOUT
O
Digital audio signal output terminal when playback mode Not used (open)
23
ADDT
I
Recording data input terminal Not used (fixed at “L”)
24
DADT
O
Playback data output to the CXD2727Q (IC300)
25
LRCK
O
L/R sampling clock signal (44.1 kHz) output to the CXD2727Q (IC300)
26
XBCK
O
Bit clock signal (2.8224 MHz) output to the CXD2727Q (IC300)
27
FS256
O
Clock signal (11.2896 MHz) output terminal Not used (open)
28
DVDD
—
Power supply terminal (+3.3V) (digital system)
29 to 32
A03 to A00
O
Address signal output to the D-RAM (IC307)
33
A10
O
Address signal output to the external D-RAM Not used (open)
34 to 38
A04 to A08
O
Address signal output to the D-RAM (IC307)
39
A11
O
Address signal output to the external D-RAM Not used (open)
40
DVSS
—
Ground terminal (digital system)
41
XOE
O
Output enable signal output to the D-RAM (IC307) “L” active
42
XCAS
O
Column address strobe signal output to the D-RAM (IC307) “L” active
43
A09
O
Address signal output to the D-RAM (IC307)
44
XRAS
O
Row address strobe signal output to the D-RAM (IC307) “L” active
45
XWE
O
Write enable signal output to the D-RAM (IC307) “L” active
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR, EFM/ACIRC ENCODER/DECODER,
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER, 2M BIT D-RAM)
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER, 2M BIT D-RAM)
55
Pin No.
Pin Name
I/O
Description
46
D1
I/O
47
D0
I/O
48
D2
I/O
49
D3
I/O
50
MVCI
I
Digital in PLL oscillation input from the external VCO Not used (fixed at “L”)
51
ASYO
O
Playback EFM full-swing output terminal
52
ASYI
I (A)
Playback EFM asymmetry comparator voltage input terminal
53
AVDD
—
Power supply terminal (+3.3V) (analog system)
54
BIAS
I (A)
Playback EFM asymmetry circuit constant current input terminal
55
RFI
I (A)
Playback EFM RF signal input from the CXA2523AR (IC302)
56
AVSS
—
Ground terminal (analog system)
57
PDO
O (3)
Phase comparison output for clock playback analog PLL of the playback EFM Not used (open)
58
PCO
O (3)
Phase comparison output for master clock of the recording/playback EFM master PLL
59
FILI
I (A)
Filter input for master clock of the recording/playback master PLL
60
FILO
O (A)
Filter output for master clock of the recording/playback master PLL
61
CLTV
I (A)
Internal VCO control voltage input of the recording/playback master PLL
62
PEAK
I (A)
Light amount signal (RF/ABCD) peak hold input from the CXA2523AR (IC302)
63
BOTM
I (A)
Light amount signal (RF/ABCD) bottom hold input from the CXA2523AR (IC302)
64
ABCD
I (A)
Light amount signal (ABCD) input from the CXA2523AR (IC302)
65
FE
I (A)
Focus error signal input from the CXA2523AR (IC302)
66
AUX1
I (A)
Auxiliary signal (I
3
signal/temperature signal) input terminal Not used (fixed at “H”)
67
VC
I (A)
Middle point voltage (+1.65V) input from the CXA2523AR (IC302)
68
ADIO
O (A)
Monitor output of the A/D converter input signal Not used (open)
69
AVDD
—
Power supply terminal (+3.3V) (analog system)
70
ADRT
I (A)
A/D converter operational range upper limit voltage input terminal (fixed at “H” in this set)
71
ADRB
I (A)
A/D converter operational range lower limit voltage input terminal (fixed at “L” in this set)
72
AVSS
—
Ground terminal (analog system)
73
SE
I (A)
Sled error signal input from the CXA2523AR (IC302)
74
TE
I (A)
Tracking error signal input from the CXA2523AR (IC302)
75
AUX2
I (A)
Auxiliary signal input terminal Light amount signal input from the CXA2523AR (IC302)
76
DCHG
I (A)
Connected to the +3.3V power supply
77
APC
I (A)
Error signal input for the laser automatic power control Not used (fixed at “L”)
78
ADFG
I
ADIP duplex FM signal (22.05 kHz
±
1 kHz) input from the CXA2523AR (IC302)
79
F0CNT
O
Filter f0 control signal output terminal Not used (open)
80
XLRF
O
Serial data latch pulse signal output terminal Not used (open)
81
CKRF
O
Serial data transfer clock signal output terminal Not used (open)
82
DTRF
O
Writing serial data output terminal Not used (open)
83
APCREF
O
Control signal output to the reference voltage generator circuit for the laser automatic power
control
control
84
LDDR
O
PWM signal output for the laser automatic power control Not used (open)
85
TRDR
O
Tracking servo drive PWM signal (–) output to the BH6511FS (IC303)
86
TFDR
O
Tracking servo drive PWM signal (+) output to the BH6511FS (IC303)
87
DVDD
—
Power supply terminal (+3.3V) (digital system)
88
FFDR
O
Focus servo drive PWM signal (+) output to the BH6511FS (IC303)
89
FRDR
O
Focus servo drive PWM signal (–) output to the BH6511FS (IC303)
90
FS4
O
Clock signal (176.4 kHz) output terminal (X’tal system) Not used (open)
Two-way data bus with the D-RAM (IC307)
56
Pin No.
Pin Name
I/O
Description
91
SRDR
O
Sled servo drive PWM signal (–) output to the BH6511FS (IC303)
92
SFDR
O
Sled servo drive PWM signal (+) output to the BH6511FS (IC303)
93
SPRD
O
Spindle servo drive PWM signal (–) output to the BH6511FS (IC303)
94
SPFD
O
Spindle servo drive PWM signal (+) output to the BH6511FS (IC303)
95
FGIN
I
Not used (fixed at “L”)
96
TEST1
I
97
TEST2
I
Input terminal for the test (fixed at “L”)
98
TEST3
I
99
DVSS
—
Ground terminal (digital system)
100
EFMO
O
EFM signal output terminal when recording mode Not used (open)
* I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.
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