Sony CDX-V60 Service Manual ▷ View online
– 21 –
Pin No.
Pin Name
I/O
Function
40
RST
I
System reset signal input terminal “L”: reset
41
VSS
—
Ground terminal
42
XTAL
O
System clock output terminal (12 MHz)
43
EXTAL
I
System clock input terminal (12 MHz)
44
NIL
I
Not used in this set (fixed at “H”)
45
NIL
I
Not used in this set (fixed at “H”)
46
O DATA
O
Outputs the data signal to on screen display controller (IC208)
47
O CLK
O
Outputs the clock signal to on screen display controller (IC208)
48
O CS
O
Outputs the chip select signal to on screen display controller (IC208)
49
G DEN
O
Outputs the disc information display switching signal to CD graphic decoder (IC281)
“H”: background color, “L”: disc information display enabled
“H”: background color, “L”: disc information display enabled
50
CDG RESET
O
Outputs the reset signal to CD graphic decoder (IC281) “L”: reset
51
G MUTE
O
Outputs the mute signal to CD graphic decoder (IC281)
“H”: active, “L”: subcode data input disabled
“H”: active, “L”: subcode data input disabled
52
AVSS
—
Ground terminal (for A/D input)
53
AVREF
I
Reference voltage input terminal (+5V) (for A/D input)
54
AVDD
—
Power supply terminal (+5V) (for A/D input)
55
CDG
I
Inputs the CD graphic disc detection signal from CD graphic decoder (IC281)
“H” is input when using CD graphic disc
“H” is input when using CD graphic disc
56
GFS
I
Inputs the guard frame sync signal from CXD2515Q (IC12) “L”: NG, “H”: OK
57
FOK
I
Inputs the focus OK signal from CXD2515Q (IC12) “L”: NG, “H”: OK
58
SENS
I
Inputs the count sense signal from CXD2515Q (IC12)
59
NIL
I
Not used in this set (fixed at “L”)
60
EHS
I
Inputs the elevator height detection (RV601) (analog input)
61
H TEMP
I
Inputs the temperature detection thermistor (TH101) (analog input)
Used for high temperature detection data input
Used for high temperature detection data input
62
NIL
I
Not used in this set (fixed at “L”)
63
POS. SW
I
Inputs the magazine eject completion detection switch (SW502) “L”: ejection completed
64
END. SW
I
Inputs the tray operation completion detection switch (SW402) “L”: load/save completed
65
DISC. SW
I
Inputs the disc detection switch (SW401) “L”: disc is present
66
CHK. SW
I
Inputs the chucking operation completion detection switch (SW302)
“L”: chucking completed
“L”: chucking completed
67
D8CM
I
Inputs disc size (8 cm/12 cm) detection from photosensor (Q501) “L”: 12 cm, “H”: 8 cm
68
EEINT
I
Not used in this set (fixed at “H”)
69
D/A SELECT
I
Not used in this set (fixed at “H”)
70
SAFETY
I
Inputs the parking brake on/off “L”: safety is reset
71
NIL
O
Not used in this set (open)
72
NIL
O
Not used in this set (open)
73
VD DS
O
Outputs the write/read strobe signal to MPEG audio/video decoder (IC201)
74
HSEL2
O
Outputs the command select signal (2) to MPEG audio/video decoder (IC201)
75
HSEL1
O
Outputs the command select signal (1) to MPEG audio/video decoder (IC201)
76
HSEL0
O
Outputs the command select signal (0) to MPEG audio/video decoder (IC201)
77
SCORE
I
Inputs the subcode sync (S0+S1) detection signal from CXD2515Q (IC12)
78
VD INIT
I
Inputs the interrupt signal from MPEG audio/video decoder (IC201)
79
SI
I
Inputs the data signal from audio bus interface (IC702)
80
SO
O
Outputs the data signal to audio bus interface (IC702)
81
SCK
I
Inputs the data transfer clock from audio bus interface (IC702)
– 22 –
Pin No.
Pin Name
I/O
Function
82
VD ACK
I
Inputs the acknowledge from MPEG audio/video decoder (IC201)
“L”: data transfer from MPEG audio/video decoder (IC201) completed
“L”: data transfer from MPEG audio/video decoder (IC201) completed
83
CFLEVEL
I
Inputs the coded data FIFO level status from MPEG audio/video decoder (IC201)
“L”: blank over 44 bytes
“L”: blank over 44 bytes
84
SQCK
O
Outputs the subcode Q data reading clock to CXD2515Q (IC12)
85
SIRCS
I
Inputs the remote control signal from audio bus system (for sony bus)
86
TEX
I
Not used in this set (fixed at “L”)
87
TX
O
Not used in this set (open)
88
VSS
—
Ground terminal
89
VDD
—
Power supply terminal (+5V)
90
N.C.
I
Not used in this set (fixed at “H”)
91
CD G/VCD
O
Outputs the CD graphic output/video CD play output selection signal to MPEG audio/video
decoder (IC201), data selector (IC108), and video amplifier (IC207)
decoder (IC201), data selector (IC108), and video amplifier (IC207)
92
MLAT
O
Outputs the latch signal to D/A converter (IC601)
93
VCD RESET
O
Outputs the reset signal to MPEG audio/video decoder (IC201) “L”: reset
94
3.3V SW
O
Outputs the power supply circuit on/off control signal to MPEG audio/video decode (IC201)
“H”: power on
“H”: power on
95
NAVI SW
O
Outputs the power on/off control signal “L”: power on Not used in this set (open)
96
CLD
O
Serial data signal output terminal Not used in this set (open)
97
CKI
O
Outputs the clock to D/A converter (IC601)
98
CDI
O
Outputs the load to D/A converter (IC601)
99
CD ON
O
Outputs the servo system power on/off control signal “L”: power on
100
SYSTEM ON
O
Outputs the main system power on/off control signal “H”: power on
– 23 –
•
MAIN BOARD IC281 LC7872E (CD GRAPHIC DECODER)
Pin No.
Pin Name
I/O
Function
1
S1
I
Selects the digital signal processing IC for CD Fixed at “H” in this set
2
S2
I
Selects the digital signal processing IC for CD Fixed at “H” in this set
3
EXCK
O
Outputs the subcode P-W reading clock to CXD2515Q (IC12)
4
WFCK
I
Inputs the write frame clock from CXD2515Q (IC12)
5
SBSO
I
Inputs the subcode P-W serial data signal from CXD2515Q (IC12)
6
SCOR
I
Inputs the subcode sync (S0+S1) detection signal from CXD2515Q (IC12)
7
VDD1
—
Power supply terminal (+5V) (digital system)
8
CE
I
Used as chip enable input at serial input/output Not used in this set (fixed at “L”)
9
DO
O
Outputs serial data signal Not used in this set (open)
10
DI
I
Inputs serial data signal Not used in this set (fixed at “L”)
11
CL
I
Inputs the clock at serial data input/output Not used in this set (fixed at “L”)
12
MUTE
I
Inputs the mute signal from system controller (IC101) “H”: active
“H”: subcode data input disabled
“H”: subcode data input disabled
13
VSS1
—
Ground terminal (digital system)
14
WE
O
Outputs the write enable signal to D-RAM (IC282)
15
RAS
O
Outputs the row address strobe signal to D-RAM (IC282)
16
A0
O
Outputs the address signal to D-RAM (IC282)
17
A1
O
Outputs the address signal to D-RAM (IC282)
18
A2
O
Outputs the address signal to D-RAM (IC282)
19
A3
O
Outputs the address signal to D-RAM (IC282)
20
A4
O
Outputs the address signal to D-RAM (IC282)
21
A5
O
Outputs the address signal to D-RAM (IC282)
22
A6
O
Outputs the address signal to D-RAM (IC282)
23
A7
O
Outputs the address signal to D-RAM (IC282)
24
GB0
I/O
Two-way data bus for D-RAM (IC282)
25
CAS
O
Outputs the column address strobe signal to D-RAM (IC282)
26
GB1
I/O
Two-way data bus for D-RAM (IC282)
27
OE
O
Outputs the output enable signal to D-RAM (IC282)
28
GB2
I/O
Two-way data bus for D-RAM (IC282)
29
GB3
I/O
Two-way data bus for D-RAM (IC282)
30
CB
I
Inputs the video output mode selection signal
“L”: normal output mode, “H”: color bar output mode (fixed at “L”)
“L”: normal output mode, “H”: color bar output mode (fixed at “L”)
31
CDGM
O
Outputs the CD graphic disc detection signal to system controller (IC101)
“H”is output when CD graphic disc is used
“H”is output when CD graphic disc is used
32
TRANS0
O
Outputs the transparency digital signal Not used in this set (open)
33
TRANS1
O
Outputs the transparency digital signal Not used in this set (open)
34
TRANS2
O
Outputs the transparency digital signal Not used in this set (open)
35
TRANS3
O
Outputs the transparency digital signal Not used in this set (open)
36
TRANS4
O
Outputs the transparency digital signal Not used in this set (open)
37
TRANS5
O
Outputs the transparency digital signal Not used in this set (open)
38
VSS2
—
Ground terminal (composite video D/A converter system)
39
VDD2
—
Power supply terminal (+5V) (composite video D/A converter system)
40
BIAS
O
Connect a capacitor for removing ripple
41
VIDEO OUT
O
Outputs the composite video signal (8-bit D/A converter output)
42
TEST
I
Test terminal (open)
– 24 –
Pin No.
Pin Name
I/O
Function
43
LINE
I
44
FSCIN
I
Inputs the subcarrier clock signal Not used in this set (open)
45
VSYNC
O
Outputs the vertical sync signal Not used in this set (open)
46
TEST1
I
Test terminal (open)
47
YS
O
Outputs the superimpose control signal Not used in this set (open)
48
CSYNC
O
Outputs the composite sync signal Not used in this set (open)
49
4FSC2
I
Inputs external clock at superimpose Not used in this set (open)
50
EFLG
O
Outputs the error status monitor Not used in this set (open)
51
FSX
O
Outputs the error status monitor trigger signal Not used in this set (open)
52
DEN
I
Inputs the disc information display switching signal from system controller (IC101)
“H”: background color, “L”: disc information display enabled
“H”: background color, “L”: disc information display enabled
53
PALID
I
Inputs external control signal in superimpose PAL mode Not used in this set (open)
54
HRESET
I
Inputs external control signal for horizontal timing Not used in this set (open)
55
FSC
O
Outputs the subcarrier clock to video RGB buffer (IC206)
NTSC mode: 3.579545 MHz, PAL mode: 4.433619 MHz
NTSC mode: 3.579545 MHz, PAL mode: 4.433619 MHz
56
VRESET
I
Inputs external control signal for vertical timing Not used in this set (open)
57
RESET
I
Inputs the reset signal from system controller (IC101) “L”: reset
58
N/P1
I
Inputs NTSC/PAL selection signal (RGB encoder system)
“H”: NTSC, “L”: PAL (fixed at "H")
“H”: NTSC, “L”: PAL (fixed at "H")
59
N/P2
I
Inputs NTSC/PAL selection signal (CD graphic encoder system)
“H”: NTSC, “L”: PAL (fixed at "H")
“H”: NTSC, “L”: PAL (fixed at "H")
60
SON
I
Inputs the superimpose on/off control signal (fixed at "L")
61
XIN2
I
Inputs the clock (17.734476 MHz, PAL) Not used in this set (open)
62
XOUT2
O
Outputs the clock (17.734476 MHz, PAL) Not used in this set (open)
63
XIN1
I
Inputs the clock from PLL circuit (14.31818 MHz, NTSC)
64
XOUT1
O
Outputs the clock (14.31818 MHz, NTSC) Not used in this set (open)
With the N/P2 pin (pin %ª) for NTSC/PAL setting in “H” status, 263H is attained when the
signal to be input to pin $£ is “H”, or 262H when “L”. Or, with the N/P2 pin in “L” status,
312H is attained when the signal to be input to pin $£ is “H”, or 314H “L”
signal to be input to pin $£ is “H”, or 262H when “L”. Or, with the N/P2 pin in “L” status,
312H is attained when the signal to be input to pin $£ is “H”, or 314H “L”
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