Sony CDX-848X Service Manual ▷ View online
33
CDX-848X
IC203
BR24C16FJ-E2
DEVICE
ADDRESS
COMPARATOR
Y DEC
H.V. PUMP/TIMING
DATA RECOVERY
E
2
PROM
SERIAL MUX
START
STOP
LOGIC
SERIAL
CONTROL
LOGIC
DATA WORD
ADDR/COUNTER
D
OUT
/ACK
LOGIC
1
2
2
3
4
5
6
7
8
X DEC
VCC
TST
SDL
SDA
A0
A1
A2
A2
GND
COMP
LOAD
LOAD INC
R/W
EN
D
OUT
D
IN
IC301
LB1930M-TLM
1
2
3
4
5
6
7
8
9
10
VCC
IN2
S-GND
IN1
NC
NC
OUT2
NC
P-GND
OUT1
CONTROL
CIRCUIT
MOTOR
DRIVE
CIRCUIT
BUFFER
BUFFER
IC302
BA8272AFV-E2
1
2
3
4
5
6
7
8
9
10
14
13
12
11
VCC
BUS ON
LINK OFF
CLK OUT
DATA OUT
DATA IN
BUS RESET
BUS DATA
VREF
BUS CLK
GND
BUS ON IN
BUS ON OUT
RESET
RESET
SWITCH
IC304
MJM2395AF08
IC305
MJM2395AF05
2
VOUT
3
GND
1
VIN
4
CONT
CONTROL
1
2
3
26
25
28
27
23
22
21
24
7
8
9
10
20
19
4
5
6
LOW-PASS
FILTER
MODE
CONTROL
INTERFACE
SERIAL
INPUT
INTERFACE
CRYSTAL
OSCILLATOR
POWER
SUPPLY
MULTI LEVEL
∆∑
MODULATOR
8 TIME OVER
SAMPLING
DIGITAL FILTER
WITH
FUNCTION CONTROLLER
SCK
OPEN
LOW-PASS
FILTER
D/A
CONVERTER
BPZ
CONTROL
D/A
CONVERTER
11
12
13
14
15
18
17
16
LRCK
DATA
BCK
DGND
VDD
VCC2R
AGND2R
CLKO
XTI
XTO
EXTR
NC
VOUTR
AGND1
DM0
MUTE
IIS
DM1
IW0
RST
ZERO
IW1
VCC2L
AGND2L
VCC1
EXTL
NC
VOUTL
IC501
PCM1728E/2K
34
CDX-848X
6-13.
IC PIN FUNCTION DESCRIPTION
•
MAIN BOARD IC201 MB90473PFV-G-108-BNDE1 (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1, 2
RAMA5, RAMA6
O
Address signal output to the S-RAM Not used (open)
3
ELVR
O
Motor drive signal (elevator down direction) output to the elevator motor drive (IC301)
“L” active *1
“L” active *1
4
ELVF
O
Motor drive signal (elevator up direction) output to the elevator motor drive (IC301)
“L” active *1
“L” active *1
5
LOADF
O
Motor drive signal (load chucking direction) output to the chucking motor drive (IC201)
“L” active *2
“L” active *2
6
LOADR
O
Motor drive signal (save direction) output to the chucking motor drive (IC201)
“L” active *2
“L” active *2
7, 8
RAMA7, RAMA12
O
Address signal output to the S-RAM Not used (open)
9
VSS
—
Ground terminal
10
RAMA14
O
Address signal output to the S-RAM Not used (open)
11
RAMWE
O
Write enable output to the S-RAM Not used (open)
12 to15
RAMA13, RAMA8,
RAMA9, RAMA11
O
Address signal output to the S-RAM Not used (open)
16
UNI SI
I
Serial data input from the SONY bus interface (IC302)
17
UNI SO
O
Serial data output to the SONY bus interface (IC302)
18
UNI CK
I
Serial data transfer clock signal input from the SONY bus interface (IC302)
19
LEDDAT
O
Not used (open)
20
LEDCLK
O
Not used (open)
21
VCC
—
Power supply terminal (+3.3V)
22
LEDLAT
O
Not used (open)
23
CDON
O
D/A converter and servo section power supply on/off control signal output “H”: power on
24
ELVON
O
Mechanism deck section power supply on/off control signal output “H”: power on
25
RX
I
Input terminal at the flash memory data write mode Not used (open)
26
TX
O
Output terminal at the flash memory data write mode Not used (open)
27
NC
O
Not used (open)
28
EECLK
O
Serial data transfer clock signal output to the EEPROM (IC203)
29
FL BOOT
I
Flash memory data write control signal input terminal “L” active Not used (fixed at “H”)
30, 31
NC
O
Not used (open)
32
EEDAT
I/O
Two-way data bus with the EEPROM (IC203)
33
AVCC
—
Power supply terminal (+3.3V) (for A/D converter)
34
AVRH
I
Reference voltage (+3.3V) input terminal (for A/D converter)
35
AVSS
—
Ground terminal (for A/D converter)
36
EHS
I
Elevator height position detection signal input from the RV202 (elevator height sensor)
(A/D input)
(A/D input)
37
MCK
I
Input of detection signal for the fine adjustment (elevator height (address) adjustment; RV201) of
elevator height position (A/D input)
elevator height position (A/D input)
38, 39
KEY0, KEY1
I
Not used (open)
40
VSS
—
Ground terminal
41
FOK
I
Focus OK signal input from the CXD3027R (IC101) “L”: NG, “H”: OK
42
GFS
I
Guard frame sync signal input from the CXD3027R (IC101) “L”: NG, “H”: OK
43
SCLK
O
Serial data reading clock signal output to the CXD3027R (IC101)
44
SENS
I
Internal status signal (sense signal) input from the CXD3027R (IC101)
45
BUSON
I
Bus on/off control signal input from the SONY bus interface (IC302) “H”: bus on
46
BUCHK
I
Battery detection signal input “L”: battery on
35
CDX-848X
Pin No.
Pin Name
I/O
Description
47, 48
MD0, MD1
I
Setting terminal for the CPU operational mode (fixed at “H” in this set)
49
MD2
I
Setting terminal for the CPU operational mode (fixed at “L” in this set)
50
EJECT SW
I
Eject switch (SW801) input terminal “L” active
51
MAGLK SW
I
Magazine detect switch (SW201) input terminal “L”: magazine is set
52
SCOR
I
Subcode sync (S0+S1) detection signal input from the CXD3027R (IC101)
53
GRSCOR
I
Subcode sync (S0+S1) detection signal input from the D-RAM controller section on the
CXD3027R (IC101)
CXD3027R (IC101)
54
NC
O
Not used (open)
55
HS
O
Normal/high speed playback control signal output terminal
“L”: high speed playback Not used (open)
“L”: high speed playback Not used (open)
56
SQSO
I
Subcode Q data input from the CXD3027R (IC101)
57
NC
O
Not used (open)
58
SQCK
O
Subcode Q data reading clock signal output to the CXD3027R (IC101)
59
CDCLK
O
Serial data transfer clock signal output to the CXD3027R (IC101)
60
CDLAT
O
Serial data latch pulse signal output to the CXD3027R (IC101)
61
CDDAT
O
Serial data output to the CXD3027R (IC101)
62
XRST
O
System reset signal output to the CXD3027R (IC101) and D/A converter (IC501) “L”: reset
63
XQOK
O
Subcode Q OK pulse signal output to the CXD3027R (IC101) “L” active
64
XRDE
O
D-RAM read enable signal output to the CXD3027R (IC101) “L” active
65
XWRE
O
D-RAM write enable signal output to the CXD3027R (IC101) “L” active
66
EMPH
O
Emphasis control signal output to the D/A converter (IC501) “H”: emphasis on
67
MUTE
O
Audio line muting on/off control signal output “H”: muting on
68
RAMA10
O
Address signal output to the S-RAM Not used (open)
69
RAMCS
O
Chip select enable output to the S-RAM Not used (open)
70 to 74
RAMIO7 to
RAMIO3
I/O
Two-way data bus with the S-RAM Not used (open)
75
RESET
I
System reset signal input from the SONY bus interface (IC302) and reset signal generator (IC303)
“L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
“L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
76
RAMIO2
I/O
Two-way data bus with the S-RAM Not used (open)
77
X1A
O
Sub system clock output terminal Not used (open)
78
X0A
I
Sub system clock input terminal Not used (fixed at “L”)
79
VSS
—
Ground terminal
80
X0
I
Main system clock input terminal (4 MHz)
81
X1
O
Main system clock output terminal (4 MHz)
82
VCC
—
Power supply terminal (+3.3V)
83, 84
RAMIO1, RAMIO0
I/O
Two-way data bus with the S-RAM Not used (open)
85 to 88
RAMA0 to RAMA3
O
Address signal output to the S-RAM Not used (open)
89
SINGLE
I
Setting terminal for the single disc/multiple discs mode
“L”: single disc mode, “H”: multiple discs mode (fixed at “H”)
“L”: single disc mode, “H”: multiple discs mode (fixed at “H”)
90
DOUTSEL
I
Analog/digital select switch (SW701) input terminal “L”: digital, “H”: analog
91
CFSEL
I
Custom file on/off setting terminal “L”: custom file on (fixed at “L”)
92
TEXTSEL
I
CD text mode setting terminal
“L”: CD text on, “H”: does not display track name (fixed at “L”)
“L”: CD text on, “H”: does not display track name (fixed at “L”)
93
ESPSEL
I
ESP on/off setting terminal “L”: ESP on (fixed at “L”)
94
TEST
I
Test mode setting terminal “L”: test mode Not used (open)
95
MAG SW
I
Magazine in/out detect switch input terminal Not used (open)
36
CDX-848X
Pin No.
Pin Name
I/O
Description
96
SAVE SW
I
Save end detect switch (SW2) input terminal
“L”: When completion of the disc save operation
“L”: When completion of the disc save operation
97
LOAD SW
I
Chucking end detect switch (SW1) input terminal
“L”: When completion of the disc chucking operation
“L”: When completion of the disc chucking operation
98
LIM SW
I
Sled limit in detect switch (SW3) input terminal
“L”: When the optical pick-up is inner position
“L”: When the optical pick-up is inner position
99
RW SEL
O
CD-ROM/RW selection signal output “L”: CD-ROM, “H”: CD-RW
100
RAMA4
O
Address signal output to the S-RAM Not used (open)
*1 elevator motor (M104) control
STOP
ELEVATOR
UP
ELEVATOR
DOWN
BRAKE
ELVF (pin 4)
“H”
“L”
“H”
“L”
ELVR (pin 3)
“H”
“H”
“L”
“L”
Mode
Terminal
*2 chucking motor (M103) control
STOP
LOAD
CHUCKING
SAVE
BRAKE
LOADF (pin 5)
“H”
“L”
“H”
“L”
LOADR (pin 6)
“H”
“H”
“L”
“L”
Mode
Terminal
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