Sony TA-DA9000ES (serv.man2) Service Manual ▷ View online
117
TA-DA9000ES
– AMP Board –
IC1504, 1505, 1516, 1517
CXD9730Q
39
NSPMUTE
40
PGMUTE
24
OUTL1+
23
VDDL1+
22
VDDL1–
21
OUTL1–
20
VSSL1–
19
VSSL2–
OUTL2–
VDDL2–
VDDL2+
OUTL2+
VSSL2+
VSSR1+
OUTR1+
VDDR1+
VDDR1–
OUTR1–
VSSR1–
VSSR2–
18
17
16
15
14
13
12
11
10
9
8
7
6
OUTR2–
5
VDDR2–
4
VDDR2+
3
OUTR2+
2
VWELL
1
VWELR
62 EXBCK
63 CXWCK
64 XFSIIN
XFSIIN
60 EXDATAL
59 EXIOSEL
61 EXDATAR
57 CKCTL2
CKCTL2
58 BFVDD
56 CKCTL1
55 TEST2
54 TEST1
49 DSDR
50 DSDL
47 DSD128FS
48 DSD64FS
52 DSDCKSEL2
53 DSDCKIO
51 DSDCKSEL1
PWM
/THROUGH
CLOCK
GENERATOR
(SECONDARY)
CLOCK
GENERATOR
(PRIMARY)
∆∑
S g P
45 LRCK
46 FSII
43 DATA
37
SCSHIFT
38
SCDT
36
SCLATCH
35
MODE2
34
MODE1
33
DVDD
32
MCKSEL
41 INIT
44 BCK
S g P
DOWN
SAMPLING
FILTER
GAIN
CONTROL
INIT/
MUTE
SERIAL
CONTROL
RATE
CONVERTER
LINER
INTERPOLATOR
(2 TIMES)
76
XOVDD
77
XFSOUT
78
XOVSS
79
VSUBCR
73
FSOCKO
80
VSSR2+
74
FSOI
75
DVDD
68
BFVSS
69
DVSS
70
OUTSEL
71
OFLFLAG
65
CKO1
72
SFLAG
66
CKO2
67
CKO3
SYNC
XFSIIN
FSII
CKCTL1
FSII
42 SYNC
SYNC
MCKSEL
MCKSEL
CKCTL2
CKCTL1
28
XFSOIN
29
XVSS
30
VSUBX
31
DVSS
27
XVDD
26
XSUBCL
25
VSSL1+
– MOTHER Board –
IC819
M62342FP
AO1
LD
1
8
AO2
CLK
2
7
NC
DI
3
6
VCC
GND
4
5
8BIT
LATCH
10BIT
SHIFT
SHIFT
REGISTER
8BIT
SUPERIOR
SEGMENT
R-2R
8BIT
LATCH
8BIT
SUPERIOR
SEGMENT
R-2R
CHANNEL
DECODER
DECODER
118
TA-DA9000ES
– DISP Board –
IC702, 703
NJU3718G (TE2)
1
28
2
3
4
5
6
7
8
9
10
12
11
PARALLEL
DATA
OUTPUT
BUFFER
LATCH
CIRCUIT
SHIFT
REGISTER
SERIAL
DATA
OUTPUT
BUFFER
CONTROL
CIRCUIT
18
17
14
15
16
19
20
21
22
23
24
25
26
27
P9
P10
P11
P12
P13
P13
P14
VSS
P15
P16
P17
P18
P19
P20
SO
VDD
P8
P7
P6
P5
P4
P3
VSS
P2
P1
CLR
STB
CLK
DATA
13
119
TA-DA9000ES
6-81. IC PIN FUNCTION DESCRIPTION
•
DIGITAL BOARD IC2201 CXD9718Q (DSP1)
Pin No.
Pin Name
I/O
Description
1
VSS
—
Ground terminal
2
XRST
I
System reset signal input from the main system controller “L”: reset
3
EXTIN
I
Master clock signal input terminal Not used
4
FS2
I
Sampling frequency selection signal input terminal Not used
5
VDDI
—
Power supply terminal (+2.6V)
6
FS1
I
Sampling frequency selection signal input terminal Not used
7
PLOCK
O
Internal PLL lock signal output terminal Not used
8
VSS
—
Ground terminal
9
MCLK1
I
System clock input terminal (13.5 MHz)
10
VDDI
—
Power supply terminal (+2.6V)
11
VSS
—
Ground terminal
12
MCLK2
O
System clock output terminal (13.5 MHz)
13
MS
I
Master/slave setting terminal “L”: internal clock, “H”: external clock
Fixed at “L” in this set
Fixed at “L” in this set
14
SCKOUT
O
Internal system clock output terminal Not used
15
LRCKI1
I
L/R sampling clock signal (44.1 kHz) input from the digital audio interface receiver, decimation
filter and i-link interface
filter and i-link interface
16
VDDE
—
Power supply terminal (+3.3V)
17
BCKI1
I
Bit clock signal (2.8224 MHz) input from the digital audio interface receiver, decimation filter
and i-link interface
and i-link interface
18
SDI1
I
Audio serial data input from the A/D converter and decimation filter
19
LRCKO
O
L/R sampling clock signal (44.1 kHz) output to the DSP2
20
BCKO
O
Bit clock signal (2.8224 MHz) output to the DSP2
21
VSS
—
Ground terminal
22
KFSIO
I
Audio clock signal input terminal
23 to 26
SDO1 to SDO4
O
Audio serial data output to the DSP2
27
SPDIF
O
SPDIF signal output terminal Not used
28
LRCKI2
I
L/R sampling clock signal (44.1 kHz) input from the digital audio interface receiver, decimation
filter and i-link interface
filter and i-link interface
29
BCKI2
I
Bit clock signal (2.8224 MHz) input from the digital audio interface receiver, decimation filter
and i-link interface
and i-link interface
30
SDI2
I
Audio serial data input from the digital audio interface receiver, decimation filter and i-link
interface
interface
31
VSS
—
Ground terminal
32
HACN
O
Acknowledge signal output to the main system controller
33
HDIN
I
Serial data input from the main system controller
34
HCLK
I
Serial data transfer clock signal input from the main system controller
35
HDOUT
O
Serial data output to the main system controller
36
HCS
I
Chip select input from the main system controller
37
SDCLK
I
Write signal input terminal Not used
38
CLKEN
O
SD-RAM chip enable output terminal Not used
39
RAS
O
Row address strobe signal output terminal Not used
40
VDDI
—
Power supply terminal (+2.6V)
41
VSS
—
Ground terminal
42
CAS
O
Column address strobe signal output terminal Not used
43
DQM/OE0
O
Output terminal of data input/output mask Not used
120
TA-DA9000ES
Pin No.
Pin Name
I/O
Description
44
CS0
O
Chip select signal output to the S-RAM
45
WE0
O
Write enable signal output to the S-RAM
46
VDDE
—
Power supply terminal (+3.3V)
47
WMD1
I
External memory wait mode setting terminal Fixed at “H” in this set
48
VSS
—
Ground terminal
49
WMD0
I
External memory wait mode setting terminal Fixed at “H” in this set
50
PAGE2
O
External memory page selection signal output terminal Not used
51
VSS
—
Ground terminal
52, 53
PAGE1, PAGE0
O
External memory page selection signal output terminal Not used
54
BOOT
I
Boot mode control signal input terminal Not used
55
BTACT
O
Boot mode state display signal output terminal Not used
56
BST
I
Boot strap signal input from the main system controller
57
MOD1
I
Operation mode setting terminal “L”: enhanced mode, “H”: normal mode
Fixed at “H” in this set
Fixed at “H” in this set
58
MOD0
I
Operation mode setting terminal “L”: single chip mode, “H”: can not use
Fixed at “L” in this set
Fixed at “L” in this set
59
EXLOCK
I
PLL lock error signal and data error flag input from the digital audio interface receiver
60
VDDI
—
Power supply terminal (+2.6V)
61
VSS
—
Ground terminal
62, 63
A17, A16
O
Address signal output terminal Not used
64 to 66
A15 to A13
O
Address signal output to the S-RAM
67
GP10
O
Not used
68
GP9
O
Read ready signal output to the main system controller
69
GP8
I
PCM audio data input from the digital audio interface receiver or i-link system controller
70
VDDI
—
Power supply terminal (+2.6V)
71
VSS
—
Ground terminal
72 to 75
D15 to D12
I/O
Two-way data bus with the S-RAM
76
VDDE
—
Power supply terminal (+3.3V)
77 to 80
D11 to D8
I/O
Two-way data bus with the S-RAM
81
VSS
—
Ground terminal
82 to 85
A9, A12 to A10
O
Address signal output to the S-RAM
86
TDO
O
Simplicity emulation data output terminal Not used
87
TMS
I
Simplicity emulation data input start and end terminal Not used
88
XTRST
I
Simplicity emulation non-sync break signal input terminal Not used
89
TCK
I
Simplicity emulation clock signal input terminal Not used
90
TDI
I
Simplicity emulation data input terminal Not used
91
VSS
—
Ground terminal
92 to 97
A8 to A3
O
Address signal output to the S-RAM
98, 99
D7, D6
I/O
Two-way data bus with the S-RAM
100
VDDI
—
Power supply terminal (+2.6V)
101
VSS
—
Ground terminal
102 to 105
D5 to D2
I/O
Two-way data bus with the S-RAM
106
VDDE
—
Power supply terminal (+3.3V)
107, 108
D1, D0
I/O
Two-way data bus with the S-RAM
109, 110
A2, A1
O
Address signal output to the S-RAM
111
VSS
—
Ground terminal
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