Sony TA-DA9000ES (serv.man2) Service Manual ▷ View online
125
TA-DA9000ES
•
DIGITAL BOARD IC2301 CXD9722TQ (LIP SYNC ADJUST)
Pin No.
Pin Name
I/O
Description
1 to 5
D1 to D5
I/O
Two-way data bus with the SD-RAM
6
VDD
—
Power supply terminal (+3.3V)
7, 8
D6, D7
I/O
Two-way data bus with the SD-RAM
9
VSS
—
Ground terminal
10
WE
O
Write enable signal output to the SD-RAM
11
CAS
O
Column address strobe signal output to the SD-RAM
12
RAS
O
Row address strobe signal output to the SD-RAM
13
CS
O
Chip select signal output to the SD-RAM
14
CLK
O
Clock signal output to the SD-RAM
15
CKE
O
Clock enable signal output to the SD-RAM
16
VDD
—
Power supply terminal (+3.3V)
17 to 22
A11, A10, A0 to A3
O
Address signal output to the SD-RAM
23
VSS
—
Ground terminal
24 to 29
A9 to A4
O
Address signal output to the SD-RAM
30
VSS
—
Ground terminal
31
DRSO
O
Surround R-ch data output terminal Not used
32
DLSO
O
Surround L-ch data output terminal Not used
33
DEXRO
O
Not used
34
DLFEO
O
Sub woofer data output terminal Not used
35
DCO
O
Center data output terminal Not used
36
VDD
—
Power supply terminal (+3.3V)
37
DRO
O
Front R-ch data output terminal Not used
38
DLO
O
Front L-ch data output terminal Not used
39
VSS
—
Ground terminal
40
DMRO
O
Data output terminal for R-ch down mix Not used
41
DMLO
O
Data output terminal for L-ch down mix Not used
42
VSS
—
Ground terminal
43
VDD
—
Power supply terminal (+3.3V)
44
DLDRO
O
Surround back audio data output to the programmable logic device
45
CSWO
O
Center and sub woofer audio data output to the programmable logic device
46
SLSRO
O
Surround audio data output to the programmable logic device
47
FLFRO
O
Front audio data output to the programmable logic device
48
VSS
—
Ground terminal
49
SPDIFO
O
Digital audio data output terminal Not used
50
TEST1
I
Input terminal for the test
51
TRST
I
Reset signal input from terminal Not used
52
TMS
I
Mode selection signal input terminal Not used
53
TCK
I
Clock signal input terminal Not used
54
TDI
I
Serial data signal input terminal Not used
55
TDO
O
Serial data signal output terminal Not used
56
TEST2
I
Input terminal for the test
57
SPDIFI
I
Digital audio data input terminal Not used
58
VSS
—
Ground terminal
59
LRCKI
I
L/R sampling clock signal (44.1 kHz) input from the Dc cut digital filter
60
BCKI
I
Bit clock signal (2.8224 MHz) input from the Dc cut digital filter
126
TA-DA9000ES
Pin No.
Pin Name
I/O
Description
61
VDD
—
Power supply terminal (+3.3V)
62
VSS
—
Ground terminal
63
DLDRI
I
Surround back audio data input from the Dc cut digital filter
64
CSWI
I
Center and sub woofer audio data input from the Dc cut digital filter
65
SLSRI
I
Surround audio data input from the Dc cut digital filter
66
FLFRI
I
Front audio data input from the Dc cut digital filter
67
TEST3
I
Input terminal for the test
68
CLK512
I
Master clock signal input terminal
69
VSS
—
Ground terminal
70
XRST
I
Reset signal input terminal “L”: reset
71
VDD
—
Power supply terminal (+3.3V)
72
SCLK
I
Serial clock signal input from the main system controller
73
XCS
I
Chip select signal input from the main system controller
74
SI
I
Serial data input from the main system controller
75
SO
O
Serial data output to the main system controller
76
DEXRI
I
Not used
77
DMLI
I
Data input terminal for L-ch down mix Not used
78
DMRI
I
Data input terminal for R-ch down mix Not used
79
VSS
—
Ground terminal
80
PHAI
I
Clock signal input terminal Not used
81
BCKAI
I
Bit clock signal (2.8224 MHz) input terminal Not used
82
DQM
O
Not used
83
DLI
I
Front L-ch data input terminal Not used
84
DRI
O
Front R-ch data input terminal Not used
85
DCI
O
Center data input terminal Not used
86
DLFEI
O
Sub woofer data input terminal Not used
87
DLSI
O
Surround L-ch data input terminal Not used
88
DRSI
O
Surround R-ch data input terminal Not used
89
VSS
—
Ground terminal
90 to 95
D15 to D10
I/O
Two-way data bus with the SD-RAM
96
VDD
—
Power supply terminal (+3.3V)
97, 98
D9, D8
I/O
Two-way data bus with the SD-RAM
99
GND
—
Ground terminal
100
D0
I/O
Two-way data bus with the SD-RAM
127
TA-DA9000ES
•
DIGITAL BOARD IC2426 ISPLSI2032VE-110LTN44-MOD (PROGRAMMABLE LOGIC DEVICE)
Pin No.
Pin Name
I/O
Description
1
EDGE
I
Clock signal input terminal
2
BCKIN
I
Bit clock signal (2.8224 MHz) input terminal
3
BCK2IN
I
Bit clock signal (2.8224 MHz) input terminal
4
I/O
I/O
Not used
5
MCK
I
Audio clock signal input terminal
6
VCC
—
Power supply terminal (+3.3V)
7
BSCAM
I
Boundary scan enable signal input terminal Not used
8
IN 0/TDI
I
Not used
9, 10
I/O
I/O
Not used
11
BCKAOUT
O
Not used
12
MCKOUT
O
System clock signal output to the PCM/PWM processor and D/A converter
13 to 16
DIOUT_8 to
DIOUT_5
O
Audio signal output terminal Not used
17
GND
—
Ground terminal
18
IN 1/TDO
I/O
Not used
19 to 22
DIOUT_8 to
DIOUT_5
O
Audio serial data output the PCM/PWM processor and D/A converter
23 to 26
I/O
I/O
Not used
27
Y2/TCK
I
Not used
28
VCC
—
Power supply terminal (+3.3V)
29
Y1/RESET
I
Reset signal input terminal Not used
30
TMS
I
Not used
31
DATAEN
I
Not used
32
CLKSEL
I
Clock selection signal input terminal
33
FS
I
Clock signal input terminal
34
I/O
I/O
Not used
35 to 38
DATA_1 to
DATA_4
I
Audio serial data input from the lip sync adjust
39
GND
—
Ground terminal
40
GOE0
—
Global output enable signal input terminal Not used
41 to 44
DATA_5 to
DATA_8
I
Audio serial data input terminal Not used
128
TA-DA9000ES
•
DIGITAL BOARD IC2601 MB91F155-A9ES-X105 (MAIN SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
DSP CLK
O
Serial data transfer clock signal output to the DSP1
2
DSP HDIN
O
Serial data output to the DSP1
3
1BST SEL
O
Signal selection signal output terminal “L”: boot strap signal, “H”: L/R sampling clock signal
4
1XRST
O
System reset signal output to the DSP1 “L”: reset
5
1PM
O
PLL initialize signal output to the DSP1
6
1GP9
I
Read ready signal input from the DSP1
7
1BST
O
Boot strap signal output to the DSP1
8
1HCS
O
Chip select signal output to the DSP1
9
VSS
—
Ground terminal
10
1HDOUT
I
Serial data input from the DSP1
11
1HACN
I
Acknowledge signal input from the DSP1
12
2XRST
O
System reset signal output to the DSP2 “L”: reset
13
2PM
O
PLL initialize signal output to the DSP2
14
2GP3
I
Error signal input from the DSP2
15
2BST
O
Boot strap signal output to the DSP2
16
2HCS
O
Chip select signal output to the DSP2
17
2HDOUT
I
Serial data input from the DSP2
18
2HACN
I
Acknowledge signal input from the DSP2
19
2EXLOCK
O
Lock signal output to the DSP2
20
DIR-CE
O
Chip enable signal output to the digital audio interface receiver
21
DIR-DO
I
Read data input from the digital audio interface receiver
22
DIR-ERROR
I
PLL lock error signal and data error flag input from the digital audio interface receiver
23
DIR-DATAO
I
Audio serial data input terminal
24
DIR-CKST
I
Clock select transition period input from the digital audio interface receiver
25
9776-INIT
O
Initialize signal output to the Dc cut digital filter
26
VSS
—
Ground terminal
27
VCC
—
Power supply terminal (+3.3V)
28
RF-ERROR
I
RF error signal input terminal Not used
29
TA-XCS
O
Chip select signal output to the lip sync adjust
30
TA-SO
I
Serial data input from the lip sync adjust
31
DA-LAT
O
Serial data latch pulse signal output to the D/A converter
32
DA-OUT
I
Serial data input from the D/A converter
33
D595-OE
O
Output enable signal output to the data decoder
34
D595-LAT1
O
Serial data latch pulse output to the digital input/output controller
35
D595-LAT2
O
Serial data latch pulse output to the data decoder
36
COM1-CLK
O
Serial data transfer clock signal output to the digital audio interface receiver, lip sync adjust, data
decoder and D/A converter
decoder and D/A converter
37
COM1-DAT
O
Serial data output to the digital audio interface receiver, lip sync adjust, data decoder and D/A
converter
converter
38
COM2-DAT
O
Serial data output to the function switch, data decoder, LED driver, electrical volume and tuner
unit
unit
39
COM2-CLK
O
Serial data transfer clock signal output to the function switch, data decoder, LED driver, electrical
volume and tuner unit
volume and tuner unit
40
RY-595OE
O
Output enable signal output to the data decoder
41
V595/C595-OE
O
Output enable signal output to the data decoder
42
RY595-LAT
O
Serial data latch pulse output to the data decoder
