Sony TA-DA9000ES (serv.man2) Service Manual ▷ View online
121
TA-DA9000ES
Pin No.
Pin Name
I/O
Description
112
A0
O
Address signal output to the S-RAM
113
PM
I
PLL initialize signal input from the main system controller
114, 115
SDI3, SDI4
I
Audio serial data input from the decimation filter
116
SYNC
I
Sync/non-sync setting terminal “L”: sync, “H”: non-sync Fixed at “H” in this set
117
TST2
O
Output terminal for the test Not used
118
VSS
—
Ground terminal
119
TST2
O
Output terminal for the test Not used
120
VDDI
—
Power supply terminal (+2.6V)
122
TA-DA9000ES
•
DIGITAL BOARD IC2251 CXD9782R (DSP2)
Pin No.
Pin Name
I/O
Description
1
VDDI
—
Power supply terminal (+2.6V)
2
EXTIN
I
Master clock signal input terminal Not used
3, 4
WMD1, WMD0
I
External memory wait mode setting terminal Fixed at “H” in this set
5
MOD1
I
Operation mode setting terminal “L”: enhanced mode, “H”: normal mode
Fixed at “H” in this set
Fixed at “H” in this set
6
MOD0
I
Operation mode setting terminal “L”: single chip mode, “H”: can not use
Fixed at “L” in this set
Fixed at “L” in this set
7
VSS
—
Ground terminal
8
XRST
I
System reset signal input from the main system controller “L”: reset
9
VSS
—
Ground terminal
10
SCKOUT
O
Internal serial clock signal output terminal Not used
11
VDDI (PLL)
—
Power supply terminal (+2.6V) (for PLL)
12
SYNC
I
Sync/non-sync setting terminal “L”: sync, “H”: non-sync Fixed at “H” in this set
13 to 15
PAGE2 to PAGE0
O
External memory page selection signal output terminal Not used
16
PLOCK
O
Internal PLL lock signal output terminal Not used
17
BTACK
O
Boot mode state display signal output terminal Not used
18
VDDE
—
Power supply terminal (+3.3V)
19
VSS
—
Ground terminal
20 to 22
D31 to D29
I/O
Two-way data bus with the S-RAM
23
A17
O
Address signal output terminal Not used
24
VSS
—
Ground terminal
25, 26
SDO3, SDO4
O
Audio serial data output to the DC cut digital filter
27, 28
SDI1, SDI2
I
Audio serial data input from the DSP1
29
LRCKI1
I
L/R sampling clock signal (44.1 kHz) input from the DSP
30
VSS
—
Ground terminal
31, 32
D28, D27
I/O
Two-way data bus with the S-RAM
33
A16
O
Address signal output terminal Not used
34
A15
O
Address signal output to the S-RAM
35
SDI3
I
Audio serial date input from the DSP
36
L2
—
Not used
37
VDDI
—
Power supply terminal (+2.6V)
38
BCKI1
I
Bit clock signal (2.8224 MHz) input from the DSP
39
SDI4
I
Audio serial data input from the DSP
40
MS
I
Master/slave setting terminal “L”: internal clock, “H”: external clock
Fixed at “L” in this set
Fixed at “L” in this set
41, 42
A14, A13
O
Address signal output to the S-RAM
43, 44
D26, D25
I/O
Two-way data bus with the S-RAM
45
VSS
—
Ground terminal
46
BCKI2
I
Bit clock signal (2.8224 MHz) input terminal Not used
47, 48
FS2, FS1
I
Sampling frequency selection signal input terminal Not used
49
SPDIF
I
SPDIF signal input terminal Not used
50
A12
O
Address signal output to the S-RAM
51 to 53
D24 to D22
I/O
Two-way data bus with the S-RAM
54
VDDE
—
Power supply terminal (+3.3V)
55
VSS
—
Ground terminal
123
TA-DA9000ES
Pin No.
Pin Name
I/O
Description
56 to 58
D21 to D19
I/O
Two-way data bus with the S-RAM
59
A11
O
Address signal output to the S-RAM
60, 61
SDO1, SDO2
O
Audio serial data output to the DC cut digital filter
62
KFSIO
I
Audio clock signal input terminal
63
LRCKO
O
L/R sampling clock signal (44.1 kHz) output to the DC cut digital filter
64
BCKO
O
Bit clock signal (2.8224 MHz) output to the DC cut digital filter
65
VDDI
—
Power supply terminal (+2.6V)
66
VSS
—
Ground terminal
67, 68
D18, D17
I/O
Two-way data bus with the S-RAM
69, 70
A10, A9
O
Address signal output to the S-RAM
71
CAS
O
Column address strobe signal output terminal Not used
72
RAS
O
Row address strobe signal output terminal Not used
73
VDDI
—
Power supply terminal (+2.6V)
74
HDIN
I
Serial data input from the main system controller
75
HCLK
I
Serial data transfer clock signal input from the main system controller
76
HCS
I
Chip select signal input from the main system controller
77, 78
A8, A7
O
Address signal output to the S-RAM
79, 80
D16, D15
I/O
Two-way data bus with the S-RAM
81
VSS
—
Ground terminal
82
HDOUT
O
Serial data output to the main system controller
83
HACN
O
Acknowledge signal output to the main system controller
84
CS0
O
Chip select signal output to the S-RAM
85
WE0
O
Write enable signal output to the S-RAM
86
A6
O
Address signal output to the S-RAM
87 to 89
D14 to D12
I/O
Two-way data bus with the S-RAM
90
VDDE
—
Power supply terminal (+3.3V)
91
VSS
—
Ground terminal
92 to 94
D11 to D9
I/O
Two-way data bus with the S-RAM
95
A5
O
Address signal output to the S-RAM
96
VDDI
—
Power supply terminal (+2.6V)
97
TCK
I
Simplicity emulation clock signal input terminal Not used
98
TDI
I
Simplicity emulation data input terminal Not used
99
TDO
O
Simplicity emulation data input terminal Not used
100
TMS
I
Simplicity emulation data input start and end select Not used
101
XTRST
I
Simplicity emulation non-sync break signal input terminal Not used
102
VSS
—
Ground terminal
103, 104
D8, D7
I/O
Two-way data bus with the S-RAM
105, 106
A4, A3
O
Address signal output to the S-RAM
107, 108
GP10, GP9
O
Not used
109
VDDI
—
Power supply terminal (+2.6V)
110
GP8
O
Not used
111
GP7
I
L/R sampling clock signal (44.1 kHz) input terminal
112
GP6
O
Not used
113, 114
A2, A1
O
Address signal output to the S-RAM
115, 116
D6, D5
I/O
Two-way data bus with the S-RAM
117
VSS
—
Ground terminal
124
TA-DA9000ES
Pin No.
Pin Name
I/O
Description
118, 119
GP5, GP4
O
Not used
120
GP3
O
Error signal output to the main system controller
121
NC
—
Not used
122
A0
O
Address signal output to the S-RAM
123 to 125
D4 to D2
I/O
Two-way data bus with the S-RAM
126
VDDE
—
Power supply terminal (+3.3V)
127
VSS
—
Ground terminal
128, 129
D1, D0
I/O
Two-way data bus with the S-RAM
130 to 132
GP2 to GP0
O
Not used
133
SDCLK
O
SD-RAM clock signal output terminal Not used
134
CLKEN
O
SD-RAM chip enable output terminal Not used
135
DQM
O
Output terminal of data input/output mask Not used
136
EXLOCK
I
Lock signal input from the main system controller
137
VDDI
—
Power supply terminal (+2.6V)
138
VSS
—
Ground terminal
139
MCLK2
O
System clock output terminal (13.5 MHz)
140
PM
I
PLL initialize signal input from the main system controller
141
BST
I
Boot strap signal input from the main system controller
142
BOOT
I
Boot mode control signal input terminal Not used
143
TST
I
Not used
144
MCLK1
I
System clock input terminal (13.5 MHz)
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