Sony STR-DA7100ES Service Manual ▷ View online
41
STR-DA7100ES
Pin No.
Pin Name
I/O
Description
169, 170
+/– JOG1, +/– JOG2
I
Jog dial pulse input from the rotary encoder (for –/+)
171, 172
PAGE JOG1,
I
Jog dial pulse input from the rotary encoder (for MENU)
PAGE JOG2
173, 174
MAIN MENU JOG1,
I
Jog dial pulse input from the rotary encoder (for MAIN MENU)
MAIN MENU JOG2
175
VSS
-
Ground terminal
176
VCC
-
Power supply terminal (+3.3V)
42
STR-DA7100ES
ILINK BOARD IC3002 HD6432365A19FV-TAA70 (I. LINK SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1, 2
MD0, MD1
-
Not used
3, 4
VSS
-
Ground terminal
5
MD2
-
Not used
6
VCC
-
Power supply terminal (+3.3V)
7
A0
-
Not used
8 to 11
A1 to A4
O
Address signal output to the i. link interface and flash memory
12
VSS
-
Ground terminal
13 to 20
A5 to A12
O
Address signal output to the i. link interface and flash memory
21
VSS
-
Ground terminal
22 to 25
A13 to A16
O
Address signal output to the i. link interface and flash memory
26
VSS
-
Ground terminal
27 to 29
A17 to A19
O
Address signal output to the i. link interface and flash memory
30 to 33
A20 to A23
-
Not used
34
EMLE
-
Not used
35, 36
VSS
-
Ground terminal
37
TD0
-
Not used
38
NMI
-
Not used
39
VCC
-
Power supply terminal (+3.3V)
40
ARMRST
O
System reset signal output to the i. link interface “L”: reset
41 to 56
-
-
Not used
57 to 63
D0 to D6
I/O
Two-way data bus with the i. link interface and flash memory
64
VSS
-
Ground terminal
65
D7
I/O
Two-way data bus with the i. link interface and flash memory
66
VCC
-
Power supply terminal (+3.3V)
67
NC
-
Not used
68
VSS
-
Ground terminal
69 to 76
D8 to D15
I/O
Two-way data bus with the i. link interface and flash memory
77
WAIT
I
Bus wait request signal input from the i. link interface
78, 79
CS5, CS6
-
Not used
80
LWR
-
Not used
81
HWR
O
Read/write enable signal output to the i. link interface and flash memory
82
RD
O
Read data output to the i. link interface and flash memory
83
-
-
Not used
84
PLLVCC
-
Power supply terminal (+3.3V)
85
RES
I
System reset signal input from the main system controller “L”: reset
86
PLLVSS
-
Ground terminal
87
CLK
O
Serial data transfer clock signal output to the i. link interface
88
VSS
-
Ground terminal
89
XTAL
O
System clock output terminal (24.576 MHz)
90
EXTAL
I
System clock input terminal (24.576 MHz)
91, 92
VCC
-
Power supply terminal (+3.3V)
93, 94
-
-
Not used
95
VSS
-
Ground terminal
96
STBY
-
Not used
97
-
-
Not used
98
CS_MEMZ
O
Chip select signal output to the i. link interface
99, 100
VSS
-
Ground terminal
101
CS2
O
Chip select signal output to the flash memory
43
STR-DA7100ES
Pin No.
Pin Name
I/O
Description
102
CS_IOZ
O
Chip select signal output to the i. link interface
103
AVCC
-
Power supply terminal (+3.3V)
104
VREF
I
Reference voltage input terminal (+3.3V)
105
ARMINT
I
Interrupt request signal input from the i. link interface
106 to 114
-
-
Not used
115
AVSS
-
Not used
116
TCK
-
Not used
117
TMS
-
Not used
118
TDI
-
Not used
119
CTS
I
Serial data transfer clock signal input from the main system controllaer
120
RTS
O
Serial data output to the main system controllaer
121
-
-
Not used
122
TRST
-
Not used
123, 124
-
-
Not used
125
RXD1
-
Not used
126
RXD0
I
Serial data input from the main system controllaer
127
TXD1
-
Not used
128
TXD0
O
Serial data output to the main system controllaer
44
STR-DA7100ES
ILINK BOARD IC3003 TSB43CA42PGF (I. LINK INTERFACE)
Pin No.
Pin Name
I/O
Description
1
VSS
-
Ground terminal
2, 3
TESTMODE0,
-
Not used
TESTMODE1
4
VDD
-
Power supply terminal (+3.3V)
5
VCO_CLK
I
Clock signal input from the i. link DSP
6
REF_SYT
O
Signal output for phase comparison to the i. link DSP
7
DIV_VCO
O
Clock signal output for phase comparison to the i. link DSP
8
PFD
-
Not used
9
MLPCM_BCLK
O
Bit clock signal (2.8224 MHz) output to the i. link DSP
10
MLPCM_LRCK
O
L/R sampling clock (44.1 kHz) output to the i. link DSP
11 to 13
MLPCM_D0 to
O
PCM audio signal output to the i. link DSP
MLPCM_d2
14
MLPCM_A
O
PCM audio supplementary signal output to the i. link DSP
15
GPIO2
O
SA-CD sled type signal output to the i. link DSP
16
GPIO3
O
SA-CD sled type signal output to the i. link DSP
17
GPIO4
O
44 kHz clock selelct signal output to the i. link DSP
18
GPIO5
O
FSSEL signal output to the i. link DSP
19
MSPCTL
-
Not used
20
VDD
-
Power supply terminal (+3.3V)
21
VSS
-
Ground terminal
22
CPS
-
Not used
23
AVDD
-
Power supply terminal (+3.3V)
24
AGND
-
Ground terminal
25, 26
TPB0_N,TPB0_P
I/O
i.link audio signal input/output terminal
27
AGND
-
Ground terminal
28
AVDD
-
Power supply terminal (+3.3V)
29, 30
TPA0_N,TPA0_P
I/O
i.link audio signal input/output terminal
31
TPBIAS0
O
Bias control signal output terminal for i. link input
32
AVDD
-
Power supply terminal (+3.3V)
33, 34
TPB1_N,TPB1_P
I/O
i.link audio signal input/output terminal
35
AGND
-
Ground terminal
36, 37
TPA1_N,TPA1_P
I/O
i.link audio signal input/output terminal
38
TPBIAS1
O
Bias control signal output terminal for i. link input
39, 40
NC
-
Not used
41
AVDD
-
Power supply terminal (+3.3V)
42 to 44
NC
-
Not used
45
AGND
-
Ground terminal
46, 47
R1. R0
-
Not used
48
AVDD
-
Power supply terminal (+3.3V)
49, 50
FILTER0, FILTER1
-
Not used
51
PLL_VDD
-
Power supply terminal (+3.3V)
52
XI
I
System clock input terminal (24.576 MHz)
53
XO
O
System clock output terminal (24.576 MHz)
54
PLL_GND
-
Ground terminal
55
VSS
-
Ground terminal
56
VDD
-
Power supply terminal (+3.3V)
57, 58
TEST_MODE2,
-
Not used
TEST_MODE3
59
RESET
I
System reset signal input from the main system controller “L”: reset
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