Sony STR-DA7100ES Service Manual ▷ View online
45
STR-DA7100ES
Pin No.
Pin Name
I/O
Description
60
RESET_ARM
I
System reset signal input from the i. link system controller “L”: reset
61
LINK_ON
-
Not used
62
HPS
-
Not used
63
LOW_PWR_RDY
-
Not used
64
DISABLE_IF
-
Not used
65
GPIO0
O
Reload timer output to the main system controller
66
GPIO1
O
Clock mode switch signal output terminal
67
SDA
-
Not used
68
SCL
-
Not used
69
GPIO6
O
FSSEL signal output to the i. link DSP
70
GPIO7
O
Data receive start signal and reset signal output to the i. link DSP
71
GPIO8
O
SA-CD channel select signal output to the i. link DSP
72
GPIO9
I
FSTATE signal input from the i. link DSP
73
REG_EN
-
Not used
74
REG_OUT
-
Not used
75
VDD
-
Power supply terminal (+3.3V)
76
VSS
-
Ground terminal
77
TMS
-
Not used
78
TDI
-
Not used
79
TDO
-
Not used
80
TCK
-
Not used
81
TRST
-
Not used
82
ARM_TMS
-
Not used
83
ARM_TDI
-
Not used
84
ARM_TDO
-
Not used
85
UART_TXD
-
Not used
86
UART_RXD
-
Not used
87
GPIO10
I
FSTATE signal input from the i. link DSP
88
TMR WTCHDOG
-
Not used
89
MCIF_INT
O
Interrupt request signal output to the i. link system controller
90
MCIF_CS_IO
I
Chip select signal input from the i. link system controller
91
MCIF_CS_MEM
I
Chip select signal input from the i. link system controller
92
MCIF_R_NW
-
Not used
93
MCIF_STRB
-
Not used
94
MCIF_WAIT
O
Bus wait request signal output to the i. link system controller
95
MCIF_ACK
-
Not used
96
MCIF_OE
I
Read data input from the i. link system controller
97
MCIF_WE
I
Read/write enable signal input from the i. link system controller
98
MCIF_BUSCLK
I
Serial data transfer clock signal input from the i. link system controller
99, 100
MCIF_DATA0,
I/O
Two-way data bus with the i. link system controller and flash memory
MCIF_DATA1
101
VDD
-
Power supply terminal (+3.3V)
102
VSS
-
Ground terminal
103 to 114
MCIF_DATA2 to
I/O
Two-way data bus with the i. link system controller and flash memory
MCIF_DATA13
115
REG_OUT
-
Not used
116
VDD
-
Power supply terminal (+3.3V)
117
VSS
-
Ground terminal
46
STR-DA7100ES
Pin No.
Pin Name
I/O
Description
118, 119
MCIF_DATA14,
I/O
Two-way data bus with the i. link system controller and flash memory
MCIF_DATA15
120 to 129
MCIF_ADDR1 to
I
Address signal input from the i. link system controller
MCIF_ADDR10
130
VDD
-
Power supply terminal (+3.3V)
131
VSS
-
Ground terminal
132
MCIFENDIAN
-
Not used
133
MCIF_MODE0
-
Not used
134
MCIF_MODE1
-
Not used
135
MCIF_MODE2
-
Not used
136
HSDI0_60958_IN
-
Not used
137
HSDI0_AMCLK_IN
-
Not used
138
HSDI0_CLK
-
Not used
139
HSDI0_EN
-
Not used
140
HSDI0_AV
-
Not used
141
HSDI0_SYNC
-
Not used
142
HSDI0_DVALID
-
Not used
143
HSDI0_D0
-
Not used
144
HSDI0_D1
-
Not used
145
VDD
-
Power supply terminal (+3.3V)
146
VSS
-
Ground terminal
147
HSDI0_D2
-
Not used
148
HSDI0_D3
-
Not used
149
HSDI0_D4
-
Not used
150
HSDI0_D5
-
Not used
151
HSDI0_D6
-
Not used
152
HSDI0_D7
-
Not used
153
HSDI1_CLK
O
DSD audio signal transfer clock signal output to the i. link DSP
154
HSDI1_EN
-
Not used
155
HSDI1_AV
-
Not used
156
HSDI1_SYNC
O
Sync signal output for DSD audio signal to the i. link DSP
157
HSDI1_DVALID
-
Not used
158, 159
HSDI1_D0, HSDI1_D1
O
DSD audio signal output to the i. link DSP
160
REG_OUT
-
Not used
161
VDD
-
Power supply terminal (+3.3V)
162
VSS
-
Ground terminal
163 to 167
HSDI1_D2 to
O
DSD audio signal output to the i. link DSP
HSDI1_D6
168
HSDI1_D7
-
Not used
169
HSDI1_AMCLK_IN
I
Clock signal input from the i. link DSP
170
HSDI1_AMCLK_OUT
-
Not used
171
HSDI1_AUDIO_ERR
-
Not used
172
HSDI1_AUDIO_MUTE
O
Muting on/off control signal output to the i. link DSP
173
HSDI1_60958_IN
-
Not used
174
HSDI1_60958_OUT
O
SPDIF audio signal output to the i. link DSP
175
VDD
-
Power supply terminal (+3.3V)
176
VSS
-
Ground terminal
47
STR-DA7100ES
ILINK BOARD IC3014 DB-ACP401 (I. LINK DSP)
Pin No.
Pin Name
I/O
Description
1
VDDO
-
Power supply terminal (+3.3V)
2
SPDIFO
O
SPDIF audio signal output terminal
3 to 5
SDA3 to SDA1
O
Audio signal output terminal
6
SDA0
-
Not used
7
LRCKO
O
L/R sampling clock (44.1 kHz) output terminal
8
BCKO
O
Bit clock signal (2.8224 MHz) output terminal
9
AMCKO
O
Audio data transfer clock signal output terminal
10
AMCKEN
-
Not used
11
SDERRO
-
Not used
12
VSSO
-
Ground terminal
13
VDDO
-
Power supply terminal (+3.3V)
14
SDMUTE
-
Not used
15
SAPCMBCK
I
Bit clock signal (2.8224 MHz) input terminal
16
SAPCMLRCK
I
L/R sampling clock (44.1 kHz) input terminal
17 to 19 SAPCMD3 to SAPCMD1
I
Audio signal input terminal
20
SAMCKO
O
Audio data transfer clock signal output terminal
21
SADAO
-
Not used
22 to 25
SAD0 to SAD3
O
Audio signal output terminal
26
VSSCORE
-
Ground terminal
27
VDDCORE
-
Power supply terminal (+3.3V)
28, 29
SAD4, SAD5
O
Audio signal output terminal
30
SAFRO
-
Not used
31
TESTMD0
-
Not used
32
TESTMD1
-
Not used
33
PLLMD
-
Not used
34
SAPCMMD
-
Not used
35
REFCYCLE
-
Not used
36
RJMSBF
-
Not used
37
SEL512
-
Not used
38
CONT48
-
Not used
39
CLK48K
I
48 kHz clock signal input terminal
40
CLK48KI
-
Not used
41
CLK48KO
-
Not used
42
VSSO
-
Ground terminal
43
VDDO
-
Power supply terminal (+3.3V)
44
CONT44
-
Not used
45
CLK44K
I
44 kHz clock signal input terminal
46
CLK44KI
-
Not used
47
CLK44KO
-
Not used
48
SELOSC
-
Not used
49
XRESET
I
Reset signal input from the i. link interface
50
OUTPUTEN
-
Not used
51
FMODE
I
Clock mode switch signal input terminal
52, 53
SELDTYPE0,
I
SA-CD sled type signal input terminal
SELDTYPE1
54
SEL44K
I
44 kHz clock selelct signal input terminal
55, 56
FSSEL0, FSSEL1
I
FSSEL signal input terminal
57
VSSO
-
Ground terminal
58
VDDO
-
Power supply terminal (+3.3V)
48
STR-DA7100ES
Pin No.
Pin Name
I/O
Description
59
RSSTART
I
Data receive start signal input terminal
60
SACHSEL
I
SA-CD channel select signal input terminal
61
FMUTE
-
Not used
62, 63
FSTATE0, FSTATE1
O
FSTATE signal output terminal
64
FSTATE2
-
Not used
65
TDI
-
Not used
66
TDO
-
Not used
67
TMS
-
Not used
68
TCK
-
Not used
69
TRST
-
Not used
70
SANKIN
I
Audio data transfer clock signal input terminal
71
SAFRIN
I
Sync signal input terminal for DSD audio signal
72
SAD0IN
I
DSD audio signal input terminal
73
VSSCO
-
Ground terminal
74
VDDCO
-
Power supply terminal (+3.3V)
75 to 79
SAD1IN to SAD5IN
I
DSD audio signal input terminal
80
SADAIN
I
DSD audio signal input terminal
81
AMCKIN
I
Clock signal input terminal
82
SPDIFIN
I
SPDIF audio signal input terminal
83
SDMUTEIN
I
Muting on/off control signal input terminal
84
SDERRIN
-
Not used
85
VCO2O
O
Clock signal output terminal
86
VCO1O
O
Serial data transfer clock signal output terminal
87
REFSTY
I
Signal input terminal for fase comparate
88
VCOIN
I
Clock signal input terminal for phase comparison
89
VCOEN
-
Not used
90
VSSCORE
-
Ground terminal
91
VDDCORE
-
Power supply terminal (+3.3V)
92
VSSO
-
Ground terminal
93
VSSPASS
-
Ground terminal
94
VDDPASS
-
Power supply terminal (+3.3V)
95
LPOUT
-
Not used
96
LPIN
-
Not used
97
VDDO
-
Power supply terminal (+3.3V)
98
BCKIN
I
Bit clock signal (2.8224 MHz) input terminal
99
LRCKIN
I
L/R sampling clock (44.1 kHz) input terminal
100 to 102
SDA1IN to SDA3IN
I
Audio signal input terminal
103
SDA0IN
I
PCM audio supplementary signal input terminal
104
VSSO
-
Ground terminal
105
VDDO
-
Power supply terminal (+3.3V)
106 to 119
SDA0 to SDA13
O
Address signal output to the SD-RAM
120 to 127
SDD0 to SDD7
I/O
Two-way data bus with the SD-RAM
128
VSSO
-
Ground terminal
129
VDDO
-
Power supply terminal (+3.3V)
130 to 137
SDD8 to SDD15
I/O
Two-way data bus with the SD-RAM
138
SDCKE
O
Clock enable signal output to the SD-RAM
139
SDCLK
O
Clock signal output to the SD-RAM
140
SDDQM
O
Output terminal of data input/output mask
141
SDRAS
O
Row address strobe signal output to the SD-RAM
142
SDCAS
O
Column address strobe signal output to the SD-RAM
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