Sony STR-DA3500ES Service Manual ▷ View online
STR-DA3500ES
97
Pin No.
Pin Name
I/O
Description
D15
EM_OE#
O
Not used
D16
SPI0_ENA#
I
Chip enable signal input from the system controller
E1
ACLKR1
I
Bit clock signal input from the digital audio interface receiver and HDMI receiver
E2
ACLKX1
O
Bit clock signal output to the D/A converter
E3
UHPI_HD[21]
I/O
Not used
E4
DVDD
-
Power supply terminal (+3.3V) (for IO)
E5
VSS
-
Ground terminal
E6 to E11
CVDD
-
Power supply terminal (+1.26V) (for core)
E12
VSS
-
Ground terminal
E13
DVDD
-
Power supply terminal (+3.3V) (for IO)
E14
UHPI_HD[8]
I/O
Not used
E15
EM_CS[2]#
O
Not used
E16
EM_RW
O
Not used
F1
AFSR1
I
L/R sampling clock signal input from the digital audio interface receiver and HDMI receiver
F2
AFSX1
O
L/R sampling clock signal output to the D/A converter
F3, F4
UHPI_HD[19],
UHPI_HD[20]
I/O
Not used
F5 to F12
VSS
-
Ground terminal
F13, F14
UHPI_HD[10],
UHPI_HD[9]
I/O
Not used
F15
EM_CS[0]#
O
Chip select signal output to the SD-RAM
F16
EM_RAS#
O
Row address strobe signal output to the SD-RAM
G1
VSS
-
Ground terminal
G2
RESET#
I
Reset signal input from the system controller “L”: reset
G3, G4
UHPI_HD[17],
UHPI_HD[18]
I/O
Not used
G5
CVDD
-
Power supply terminal (+1.26V) (for core)
G6 to G11
VSS
-
Ground terminal
G12
CVDD
-
Power supply terminal (+1.26V) (for core)
G13, G14
UHPI_HD[12],
UHPI_HD[11]
I/O
Not used
G15
EM_BA[0]
O
Bank address signal output to the SD-RAM
G16
VSS
-
Ground terminal
H1
UHPI_HD[16]
I/O
Not used
H2
CLKIN
I
Not used
H3
VSS
-
Ground terminal
H4
UHPI_HD[31]
I/O
Not used
H5
CVDD
-
Power supply terminal (+1.26V) (for core)
H6 to H11
VSS
-
Ground terminal
H12
CVDD
-
Power supply terminal (+1.26V) (for core)
H13, H14
UHPI_HD[14],
UHPI_HD[13]
I/O
Not used
H15
EM_A[10]
O
Address signal output to the SD-RAM
H16
EM_BA[1]
O
Bank address signal output to the SD-RAM
J1
OSCVSS
-
Ground terminal for oscillator
J2
OSCIN
I
System clock input terminal (25 MHz)
J3
OSCOUT
O
System clock output terminal (25 MHz)
J4
OSCVDD
-
Power supply terminal for oscillator
J5
CVDD
-
Power supply terminal (+1.26V) (for core)
J6 to J11
VSS
-
Ground terminal
J12
CVDD
-
Power supply terminal (+1.26V) (for core)
J13
UHPI_HD[15]
I/O
Not used
J14
DVDD
-
Power supply terminal (+3.3V) (for IO)
J15, J16
EM_A[1], EM_A[0]
O
Address signal output to the SD-RAM
K1
VSS
-
Ground terminal
K2
PLLHV
-
Power supply terminal (+3.3V) (for PLL)
K3
TMS
I
Test mode selection signal input terminal (for JTAG)
K4
TRST#
I
Test reset signal input terminal (for JTAG)
K5
CVDD
-
Power supply terminal (+1.26V) (for core)
K6 to K11
VSS
-
Ground terminal
STR-DA3500ES
98
Pin No.
Pin Name
I/O
Description
K12
CVDD
-
Power supply terminal (+1.26V) (for core)
K13, K14
UHPI_HD[0],
UHPI_HD[1]
I/O
Not used
K15
EM_A[2]
O
Address signal output to the SD-RAM
K16
VSS
-
Ground terminal
L1
TDI
I
Test data input terminal (for JTAG)
L2 to L4
UHPI_HD[30] to UHPI_
HD[28]
I/O
Not used
L5 to L12
VSS
-
Ground terminal
L13, L14
UHPI_HD[3],
UHPI_HD[4]
I/O
Not used
L15, L16
EM_A[4], EM_A[3]
O
Address signal output to the SD-RAM
M1
EMU[0]#
I/O
Emulation terminal
M2
TDO
O
Test data output terminal (for JTAG)
M3
UHPI_HD[27]
I/O
Not used
M4
DVDD
-
Power supply terminal (+3.3V) (for IO)
M5
VSS
-
Ground terminal
M6 to M11
CVDD
-
Power supply terminal (+1.26V) (for core)
M12
VSS
-
Ground terminal
M13
DVDD
-
Power supply terminal (+3.3V) (for IO)
M14
UHPI_HD[2]
I/O
Not used
M15, M16
EM_A[6], EM_A[5]
O
Address signal output to the SD-RAM
N1
EMU[1]#
I/O
Emulation terminal
N2, N3
UHPI_HD[25],
UHPI_HD[26]
I/O
Not used
N4
EM_D[22]
I/O
Two-way data bus with the SD-RAM
N5
DVDD
-
Power supply terminal (+3.3V) (for IO)
N6 to N11
EM_D[18], EM_D[16],
EM_D[30], EM_D[29],
EM_D[30], EM_D[29],
EM_D[27], EM_D[25]
I/O
Two-way data bus with the SD-RAM
N12
DVDD
-
Power supply terminal (+3.3V) (for IO)
N13, N14
UHPI_HD[5],
UHPI_HD[6]
I/O
Not used
N15, N16
EM_A[8], EM_A[7]
O
Address signal output to the SD-RAM
P1
TCK
I
Test clock signal input terminal (for JTAG)
P2
UHPI_HD[24]
I/O
Not used
P3 to P7
EM_D[21] to EM_D[19],
EM_D[17], EM_D[31]
I/O
Two-way data bus with the SD-RAM
P8
DVDD
-
Power supply terminal (+3.3V) (for IO)
P9 to P11
EM_D[28], EM_D[26],
EM_D[24]
I/O
Two-way data bus with the SD-RAM
P12
EM_A[12]
O
Address signal output terminal Not used
P13
EM_DQM[2]
O
Byte enable signal output to the SD-RAM
P14
UHPI_HD[7]
I/O
Not used
P15
EM_A[11]
O
Address signal output terminal Not used
P16
EM_A[9]
O
Address signal output to the SD-RAM
R1
DVDD
-
Power supply terminal (+3.3V) (for IO)
R2
EM_D[23]
I/O
Two-way data bus with the SD-RAM
R3
EM_CAS#
O
Column address strobe signal output to the SD-RAM
R4
EM_DQM[0]
O
Byte enable signal output to the SD-RAM
R5 to R13
EM_D[6], EM_D[4],
EM_D[2], EM_D[1],
EM_D[2], EM_D[1],
EM_D[15], EM_D[13],
EM_D[12], EM_D[10],
EM_D[12], EM_D[10],
EM_D[8]
I/O
Two-way data bus with the SD-RAM
R14
EM_CLK
O
Clock signal output to the SD-RAM
R15
EM_DQM[3]
O
Byte enable signal output to the SD-RAM
R16
DVDD
-
Power supply terminal (+3.3V) (for IO)
T1
VSS
-
Ground terminal
T2
DVDD
-
Power supply terminal (+3.3V) (for IO)
T3
EM_WE#
O
Write enable signal output to the SD-RAM
STR-DA3500ES
99
Pin No.
Pin Name
I/O
Description
T4 to T6
EM_D[7], EM_D[5],
EM_D[3]
I/O
Two-way data bus with the SD-RAM
T7
VSS
-
Ground terminal
T8, T9
EM_D[0], EM_D[14]
I/O
Two-way data bus with the SD-RAM
T10
VSS
-
Ground terminal
T11, T12
EM_D[11], EM_D[9]
I/O
Two-way data bus with the SD-RAM
T13
EM_DQM[1]
O
Byte enable signal output to the SD-RAM
T14
EM_CKE
O
Clock enable signal output to the SD-RAM
T15
DVDD
-
Power supply terminal (+3.3V) (for IO)
T16
VSS
-
Ground terminal
STR-DA3500ES
100
MICON BOARD IC8003 F2602E-01-TR (XM RECEIVER)
Pin No.
Pin Name
I/O
Description
1
LSOPTXRX
-
Not used
2
VSS
-
Ground terminal
3
SCTXOUT
O
Serial data output to the system controller
4
VDD
-
Power supply terminal (+3.3V)
5
SCRXIN
I
Serial data input from the system controller
6
VSS
-
Ground terminal
7
COMMSEL
I
Command mode selection signal input terminal Not used
8
VDD
-
Power supply terminal (+3.3V)
9
XIRQ
O
Interrupt request signal output terminal Not used
10
VSS
-
Ground terminal
11
XRESET
I
Reset signal input from the system controller “L”: reset
12
SLAVESL
I
Master/slave mode selection signal input terminal
“L”: master mode, “H”: slave mode Fixed at “L” in this set
“L”: master mode, “H”: slave mode Fixed at “L” in this set
13
COMRXDIG
-
Not used
14
COMTXDIG
-
Not used
15
COMTXEN
-
Not used
16
VSS
-
Ground terminal
17
VDD
-
Power supply terminal (+3.3V)
18
COMRXP
I
XM receiver differential signal (positive) input from the XM connector
19
COMRXM
I
XM receiver differential signal (negative) input from the XM connector
20
VDD
-
Power supply terminal (+3.3V)
21
VSS
-
Ground terminal
22
COMTXM
O
XM transmitter differential signal (negative) output to the XM connector
23
COMTXP
O
XM transmitter differential signal (positive) output to the XM connector
24, 25
VSS
-
Ground terminal
26
OSCOUT
O
System clock output terminal (45.1584 MHz)
27
VDD
-
Power supply terminal (+3.3V)
28
OSCIN
I
System clock input terminal (45.1584 MHz)
29
VSS
-
Ground terminal
30
TEST
-
Not used
31
VSS
-
Ground terminal
32
HSDPDATA
-
Not used
33
VDD
-
Power supply terminal (+3.3V)
34
HSDPCLK
-
Not used
35
VSS
-
Ground terminal
36
HSDPEN
-
Not used
37
I2SDATA
O
I2S digital audio data output to the D/A converter (for XM section)
38
VSS
-
Ground terminal
39
I2SSCLK
O
I2S bit clock signal output to the D/A converter (for XM section)
40
VDD
-
Power supply terminal (+3.3V)
41
I2SLRCLK
O
I2S L/R sampling clock signal output to the D/A converter (for XM section)
42
VSS
-
Ground terminal
43
I2SOCLK
O
I2S over sample clock signal output to the D/A converter (for XM section)
44
VSS
-
Ground terminal
45
SAIICLK
-
Not used
46
VDD
-
Power supply terminal (+3.3V)
47
SAIIDATA
-
Not used
48
SAIIEN
-
Not used
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