Sony STR-DA3500ES Service Manual ▷ View online
STR-DA3500ES
85
DIGITAL VIDEO BOARD IC3202 YGV629-VZ (OSD CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
PLLVDD
-
Power supply terminal (+3.3V)
2
FILTER
I
Filter connection terminal for internal PLL
3
PLLVSS
-
Ground terminal
4
NC
-
Not used
5 to 10
PLLCTL5 to PLLCTL0
I
PLL setting terminal
11
DTCKS_N
I
Clock signal input terminal Not used
12
DTCK_IN
I
Clock signal input terminal Not used
13
VSS
-
Ground terminal
14
VDD
-
Power supply terminal (+3.3V)
15 to 22
D0 to D7
I/O
Two-way data bus with the video system controller and S-RAM
23
WAIT_N
O
Wait signal output to the video system controller
24
READY_N
O
Ready signal output terminal Not used
25
INT_N
O
Interrupt signal output to the video system controller
26
VDD
-
Power supply terminal (+3.3V)
27
VSS
-
Ground terminal
28
CS_N
I
Chip enable signal input from the video system controller
29
WR_N
I
Write enable signal input from the video system controller
30
RD_N
I
Read enable signal input from the video system controller
31 to 33
PS2 to PS0
I
Address signal input from the video system controller
34
SDOUT
O
Serial data output terminal Not used
35
SDIN
I
Serial data input terminal Not used
36
SCS_N
I
Chip select signal input terminal Not used
37
SCLK
I
Serial data transfer clock signal input terminal Not used
38
SER_N
I
CPU interface selection setting terminal Fixed at “H” in this set
39
RESET_N
I
Reset signal input from the video system controller “L”: reset
40
VSS
-
Ground terminal
41
VDD
-
Power supply terminal (+3.3V)
42
MA0
O
Address signal output terminal Not used
43 to 47
MA1 to MA5
O
Address signal output to the fl ash memory
48
VSS
-
Ground terminal
49 to 54
MA6 to MA11
O
Address signal output to the fl ash memory
55
VDD
-
Power supply terminal (+3.3V)
56
VSS
-
Ground terminal
57 to 62
MA12 to MA17
O
Address signal output to the fl ash memory
63
VSS
-
Ground terminal
64 to 70
MA18 to MA24
O
Address signal output to the fl ash memory
71
VDD
-
Power supply terminal (+3.3V)
72
VSS
-
Ground terminal
73
MWE_N
O
Write enable signal output to the fl ash memory
74
MOE_N
O
Output enable signal output to the fl ash memory
75 to 80
MD15, MD7, MD14,
MD6, MD13, MD5
I/O
Two-way data bus with the fl ash memory
81
VSS
-
Ground terminal
82
VDD
-
Power supply terminal (+3.3V)
83 to 90
MD12, MD4, MD11,
MD3, MD10, MD2,
MD9, MD1
I/O
Two-way data bus with the fl ash memory
91
VSS
-
Ground terminal
92
VDD
-
Power supply terminal (+3.3V)
93, 94
MD8, MD0
I/O
Two-way data bus with the fl ash memory
95
RAHZ_N
-
Not used
96 to 98
XTEST2 to XTEST0
-
Not used
99
VSIN_N
I
Vertical sync signal input terminal Not used
100
HSIN_N
I
Horizontal sync signal input terminal Not used
101
NC
-
Not used
102
AVDD
-
Power supply terminal (+3.3V)
103
R
O
Analog video (R) signal output terminal Not used
104
G
O
Analog video (G) signal output terminal Not used
105
B
O
Analog video (B) signal output terminal Not used
STR-DA3500ES
86
Pin No.
Pin Name
I/O
Description
106
IREF
-
Not used
107
AVSS
-
Ground terminal
108
NC
-
Not used
109
VDD
-
Power supply terminal (+3.3V)
110
VSS
-
Ground terminal
111 to 116
DR0 to DR5
O
Digital video (R) signal output to the video processor
117
VSS
-
Ground terminal
118
VDD
-
Power supply terminal (+3.3V)
119 to 124
DG0 to DG5
O
Digital video (G) signal output to the video processor
125
VSS
-
Ground terminal
126
VDD
-
Power supply terminal (+3.3V)
127to 132
DB0 to DB5
O
Digital video (B) signal output to the video processor
133
VSS
-
Ground terminal
134
FSC
-
Not used
135
YS_N
-
Not used
136
VSYNC_N
O
Vertical sync signal output to the video processor
137
HSYNC_N
O
Horizontal sync signal output to the video processor
138
BLANK_N
O
Blanking period signal output to the video processor
139
DOTCLK
O
Dot clock signal output to the video processor
140
VDD
-
Power supply terminal (+3.3V)
141
XIN
I
System clock input terminal (33.2 MHz)
142
XOUT
O
System clock output terminal (33.2 MHz)
143
VSS
-
Ground terminal
144
NC
-
Not used
STR-DA3500ES
87
Pin No.
Pin Name
I/O
Description
1 to 3
Q10 to Q8
O
Serial data output to the HDMI transceiver and video processor
4
IOGND
-
Ground terminal
5
ODCK
O
Output data clock signal output to the HDMI transceiver and video processor
6
IOVCC33
-
Power supply terminal (+3.3V)
7 to 10
Q7 to Q4
O
Serial data output to the HDMI transceiver and video processor
11
CGND
-
Ground terminal
12
CVCC18
-
Power supply terminal (+1.8V)
13 to 16
Q3 to Q0
O
Serial data output to the HDMI transceiver
17
IOGND
-
Ground terminal
18
IOVCC33
-
Power supply terminal (+3.3V)
19
DE
O
Data enable signal output to the D/A converter (for video section), HDMI transceiver and
video processor
video processor
20
HSYNC
O
Horizontal sync signal output to the HDMI transceiver and video processor
21
VSYNC
O
Vertical sync signal output to the video system controller, HDMI transceiver and video pro-
cessor
cessor
22
EVNODD
-
Not used
23
CGND
-
Ground terminal
24, 25
CVCC18
-
Power supply terminal (+1.8V)
26
CSDA
I/O
I2C data bus with the video system controller, D/A converter (for video section), EEPROM
and HDMI transceiver
and HDMI transceiver
27
CSCL
I
I2C clock signal input from the video system controller
28
DSDA1
I/O
I2C data bus with the HDMI IN 1 connector and EEPROM
29
DSCL1
I
I2C clock signal input from the HDMI IN 1 connector
30
R1PWR5V
I
Power supply voltage (+5V) input from the HDMI IN 1 connector
31
IOGND
-
Ground terminal
32
IOVCC33
-
Power supply terminal (+3.3V)
33
DSDA0
I/O
I2C data bus with the HDMI input selector and EEPROM
34
DSCL0
I
I2C clock signal input from the HDMI input selector
35
R0PWR5V
I
Power supply voltage (+5V) input from the HDMI connector
36
AGND
-
Ground terminal
37
AVCC18
-
Power supply terminal (+1.8V)
38
AVCC33
-
Power supply terminal (+3.3V)
39
R0XC–
I
TMDS clock (negative) signal input from the HDMI input selector
40
R0XC+
I
TMDS clock (positive) signal input from the HDMI input selector
41
AGND
-
Ground terminal
42
AVCC33
-
Power supply terminal (+3.3V)
43
R0X0–
I
TMDS data (negative) input from the HDMI input selector
44
R0X0+
I
TMDS data (positive) input from the HDMI input selector
45
AGND
-
Ground terminal
46
AVCC33
-
Power supply terminal (+3.3V)
47
R0X1–
I
TMDS data (negative) input from the HDMI input selector
48
R0X1+
I
TMDS data (positive) input from the HDMI input selector
49
AGND
-
Ground terminal
50
AVCC33
-
Power supply terminal (+3.3V)
51
R0X2–
I
TMDS data (negative) input from the HDMI input selector
52
R0X2+
I
TMDS data (positive) input from the HDMI input selector
53
AGND
-
Ground terminal
54
AVCC18
-
Power supply terminal (+1.8V)
55
RSVDNC
-
Not used
56
AVCC33
-
Power supply terminal (+3.3V)
57
R1XC–
I
TMDS clock (negative) signal input from the HDMI IN 1 connector
58
R1XC+
I
TMDS clock (positive) signal input from the HDMI IN 1 connector
59
AGND
-
Ground terminal
60
AVCC33
-
Power supply terminal (+3.3V)
61
R1X0–
I
TMDS data (negative) input from the HDMI IN 1 connector
62
R1X0+
I
TMDS data (positive) input from the HDMI IN 1 connector
63
AGND
-
Ground terminal
64
AVCC33
-
Power supply terminal (+3.3V)
65
R1X1–
I
TMDS data (negative) input from the HDMI IN 1 connector
DIGITAL VIDEO BOARD IC3506 SII9135CTU (HDMI RECEIVER)
STR-DA3500ES
88
Pin No.
Pin Name
I/O
Description
66
R1X1+
I
TMDS data (positive) input from the HDMI IN 1 connector
67
AGND
-
Ground terminal
68
AVCC33
-
Power supply terminal (+3.3V)
69
R1X2–
I
TMDS data (negative) input from the HDMI IN 1 connector
70
R1X2+
I
TMDS data (positive) input from the HDMI IN 1 connector
71
AGND
-
Ground terminal
72
AVCC18
-
Power supply terminal (+1.8V)
73
IOGND
-
Ground terminal
74
IOVCC33
-
Power supply terminal (+3.3V)
75
MUTEOUT
O
Audio muting control signal output terminal
76, 77
RSVDNC
-
Not used
78
SPDIF
O
S/PDIF signal output to the digital audio interface receiver and HDMI transceiver
79
CGND
-
Ground terminal
80
CVCC18
-
Power supply terminal (+1.8V)
81 to 84
SD0 to SD3
O
PCM audio signal output to the HDMI transceiver and DSP
85
WS
O
L/R sampling clock signal output to the HDMI transceiver, DSP and system controller
86
SCK
O
Bit clock signal output to the HDMI transceiver and DSP
87
IOGND
-
Ground terminal
88
IOVCC33
-
Power supply terminal (+3.3V)
89
MCLK
O
Master clock signal output to the HDMI transceiver and DSP
90
CGND
-
Ground terminal
91
CVCC18
-
Power supply terminal (+1.8V)
92
DVCC18
-
Power supply terminal (+1.8V)
93
DGND2
-
Ground terminal
94
XTALOUT
O
System clock output terminal (28.322 MHz)
95
XTALIN
I
System clock input terminal (28.322 MHz)
96
XTALVCC
-
Power supply terminal (+3.3V)
97
REGVCC
-
Power supply terminal (+3.3V)
98
RSVDNC
-
Not used
99
RSVDL
-
Not used
100
RESET#
I
Reset signal input from the video system controller “L”: reset
101
SCDT
-
Not used
102
INT
O
Interrupt signal output to the video system controller
103
IOGND
-
Ground terminal
104
IOVCC33
-
Power supply terminal (+3.3V)
105
CI2CA
-
Not used
106
CGND
-
Ground terminal
107
CVCC18
-
Power supply terminal (+1.8V)
108 to 111
Q35 to Q32
O
Serial data output to the HDMI transceiver and video processor
112
IOGND
-
Ground terminal
113
IOVCC33
-
Power supply terminal (+3.3V)
114 to 117
Q31 to Q28
O
Serial data output to the HDMI transceiver and video processor
118
CGND
-
Ground terminal
119
CVCC18
-
Power supply terminal (+1.8V)
120 to 123
Q27 to Q24
O
Serial data output to the HDMI transceiver
124
IOGND
-
Ground terminal
125
IOVCC33
-
Power supply terminal (+3.3V)
126 to 129
Q23 to Q20
O
Serial data output to the HDMI transceiver and video processor
130
CGND
-
Ground terminal
131
CVCC
-
Power supply terminal (+1.8V)
132 to 135
Q19 to Q16
O
Serial data output to the HDMI transceiver and video processor
136
IOGND
-
Ground terminal
137
IOVCC33
-
Power supply terminal (+3.3V)
138 to 141
Q15 to Q12
O
Serial data output to the HDMI transceiver
142
CGND
-
Ground terminal
143
CVCC18
-
Power supply terminal (+1.8V)
144
Q11
O
Serial data output to the HDMI transceiver and video processor
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