Sony STR-DA3500ES Service Manual ▷ View online
STR-DA3500ES
93
Pin No.
Pin Name
I/O
Description
M4
IPCLK2
I
Dot clock signal input from the OSD controller
M10 to
M17
D_GND
-
Ground terminal
M23
IO_3.3V
-
Power supply terminal (+3.3V)
M24, M25
LVDS_GND
-
Ground terminal
M26
LVDS_3.3V
-
Power supply terminal (+3.3V)
N1
IPCLK0
I
Clock signal input terminal Not used
N2
DIP_RAW_HS_CS
-
Not used
N3
DIP_AODD
-
Not used
N4
DIP_BODD
-
Not used
N10 to
N17
D_GND
-
Ground terminal
N23 to
N26
PD0 to PD3
I/O
Serial data input from the HDMI receiver and serial data output to the HDMI transceiver
P1 to P3
ADATA2 to ADATA0
-
Not used
P4
IPCLK1
I
Clock signal input terminal Not used
P10 to P17
D_GND
-
Ground terminal
P23
IO_3.3V
-
Power supply terminal (+3.3V)
P24
DCLK
I
Output data clock signal input from the HDMI receiver
P25
DHS
I
Horizontal sync signal input from the HDMI receiver
P26
DEN
I
Data enable signal input from the HDMI receiver
R1 to R4
ADATA6 to ADATA3
-
Not used
R10 to
R17
D_GND
-
Ground terminal
R23
JTAG_BS_TDI
-
Not used
R24
JTAG_BS_RST
-
Not used
R25
JTAG_BS_TCK
-
Not used
R26
DVS
I
Vertical sync signal input from the HDMI receiver
T1 to T4
ADATA10 to ADATA7
-
Not used
T10
D_GND
-
Ground terminal
T11
CORE_1.8V
-
Power supply terminal (+1.8V)
T12 to T15
D_GND
-
Ground terminal
T16, T17
CORE_1.8V
-
Power supply terminal (+1.8V)
T23
IO_3.3V
-
Power supply terminal (+3.3V)
T24
JTAG_BS_TMS
-
Not used
T25
JTAG_BS_TDO
-
Not used
T26
GPIO_44
-
Not used
U1 to U4
ADATA14 to ADATA11
-
Not used
U10, U11
CORE_1.8V
-
Power supply terminal (+1.8V)
U12 to
U15
D_GND
-
Ground terminal
U16, U17
CORE_1.8V
-
Power supply terminal (+1.8V)
U23, U24
PWM1, PWM2
-
Not used
U25
PPWR
-
Not used
U26
PBIAS
-
Not used
V1 to V4
ADATA18 to ADATA15
-
Not used
V23
IO_3.3V
-
Power supply terminal (+3.3V)
V24
PWM0
-
Not used
V25
SLAVE_SDA
-
Not used
V26
SLAVE_SCL
-
Not used
W1 to W4
ADATA22 to ADATA19
-
Not used
W23
OCM_INT1
-
Not used
W24
OCM_TIMER1
-
Not used
W25
OCM_UDI_0
-
Not used
W26
ODM_UDO_0
-
Not used
Y1
AVS
-
Not used
Y2
AHS
-
Not used
Y3
AHREF_DE
-
Not used
Y4
ADATA23
-
Not used
Y23
IO_3.3V
-
Power supply terminal (+3.3V)
STR-DA3500ES
94
Pin No.
Pin Name
I/O
Description
Y24
OCM_INT2
-
Not used
Y25
VGA1_SDA
-
Not used
Y26
VGA1_SCL
-
Not used
AA1
NC
-
Not used
AA2 to
AA4
DGND_ADC
-
Ground terminal
AA23
MSTR0_SDA
I/O
Two-way data bus with the EEPROM
AA24
MSTR0_SCL
O
Serial clock signal output to the EEPROM
AA25
VGA0_SDA
-
Not used
AA26
VGA0_SCL
-
Not used
AB1
A1P
I
Video signal (PR/CR) input from the video input selector (for component video signal)
AB2
SV1P
-
Not used
AB3
AGND_ADC
-
Ground terminal
AB4
ADC_1.8V
-
Power supply terminal (+1.8V)
AB23
IO_3.3V
-
Power supply terminal (+3.3V)
AB24
IRO
-
Not used
AB25
MSTR2_SDA
I/O
Not used
AB26
MSTR2_SCL
O
Not used
AC1
C1P
I
Video signal input (Y) from the video input selector (for component video signal)
AC2
B1P
I
Video signal (PB/CB) input from the video input selector (for component video signal)
AC3
AGND_ADC
-
Ground terminal
AC4, AC5
ADC_1.8V
-
Power supply terminal (+1.8V)
AC6
AGND_ADC
-
Ground terminal
AC7
VOUT2
-
Not used
AC8
AGND_ADC
-
Ground terminal
AC9
LBADC_3.3V
-
Power supply terminal (+3.3V)
AC10
LBADC_IN4
-
Not used
AC11
LBADC_GND
-
Ground terminal
AC12
AVSIN_DATA
-
Not used
AC13
EXTOSD_HS
-
Not used
AC14
IO_3.3V
-
Power supply terminal (+3.3V)
AC15
OCMADDR18
O
Address signal output to the fl ash memory
AC16
IO_3.3V
-
Power supply terminal (+3.3V)
AC17
OCMADDR11
O
Address signal output to the fl ash memory
AC18
IO_3.3V
-
Power supply terminal (+3.3V)
AC19
OCMADDR4
O
Address signal output to the fl ash memory
AC20
IO_3.3V
-
Power supply terminal (+3.3V)
AC21
OCMDATA13
I/O
Two-way data bus with the fl ash memory
AC22
IO_3.3V
-
Power supply terminal (+3.3V)
AC23
OCMDATA6
I/O
Two-way data bus with the fl ash memory
AC24
OCM_CS2N
O
Chip select signal output terminal Not used
AC25
OCN_RE_N
O
Read enable signal output to the fl ash memory
AC26
OCN_WE_N
O
Write enable signal output to the fl ash memory
AD1
AN
-
Not used
AD2
AGND_ADC
-
Ground terminal
AD3 to
AD5
ADC1_3.3V
-
Power supply terminal (+3.3V)
AD6, AD7
ADC2_3.3V
-
Power supply terminal (+3.3V)
AD8
AGND_ADC
-
Ground terminal
AD9
RESET
I
Reset signal input from the video system controller “L”: reset
AD10
LBADC_IN3
-
Not used
AD11
LBADC_RETURN
-
Not used
AD12
AVSIN_WORDSEL
-
Not used
AD13
EXTOSD_VS
-
Not used
AD14
AVSOUT_DATA
-
Not used
AD15 to
AD20
OCMADDR19,
OCMADDR15,
OCMADDR12,
OCMADDR15,
OCMADDR12,
OCMADDR8,
OCMADDR5,
OCMADDR5,
OCMADDR1
O
Address signal output to the fl ash memory
STR-DA3500ES
95
Pin No.
Pin Name
I/O
Description
AD21 to
AD23
OCMDATA14, OCMDA-
TA10, OCMDATA7
I/O
Two-way data bus with the fl ash memory
AD24
ROM_CS_N
O
Chip enable signal output to the fl ash memory
AD25,
AD26
OCM_CS0N,
OCM_CS1N
O
Chip select signal output terminal Not used
AE1
SV2P
-
Not used
AE2
B2P
I
Video signal input terminal Not used
AE3
AGND_ADC
-
Ground terminal
AE4
SV3P
-
Not used
AE5
B3P
I
Video signal input terminal Not used
AE6
AGND_ADC
-
Ground terminal
AE7
SV4P
-
Not used
AE8
BN2
-
Not used
AE9
AGND_ADC
-
Ground terminal
AE10,
AE11
LBADC_IN2,
LBADC_IN6
-
Not used
AE12
AIP_RAW_VS
-
Not used
AE13
AVSOUT_SCL
-
Not used
AE14
AVSOUT_WORDSEL
-
Not used
AE15 to
AE20
OCMADDR20,
OCMADDR16,
OCMADDR13,
OCMADDR16,
OCMADDR13,
OCMADDR9,
OCMADDR6,
OCMADDR6,
OCMADDR2
O
Address signal output to the fl ash memory
AE21 to
AE26
OCMDATA15,
OCMDATA11,
OCMDATA8,
OCMDATA2 to
OCMDATA0
I/O
Two-way data bus with the fl ash memory
AF1
A2P
I
Video signal input terminal Not used
AF2
C2P
I
Video signal input terminal Not used
AF3
BN
-
Not used
AF4
A3P
I
Video signal (CVBS) input from video input selector (for component video signal)
AF5
C3P
I
Video signal input terminal Not used
AF6
CN
-
Not used
AF7
AN2
-
Not used
AF8
CN2
-
Not used
AF9
SVN
-
Not used
AF10,
AF11
LBADC_IN1,
LBADC_IN5
-
Not used
AF12
AIP_RAW_HS_CS
-
Not used
AF13
EXTOSD_CLK
-
Not used
AF14
AVSIN_SCL
-
Not used
AF15 to
AF20
OCMADDR21,
OCMADDR17,
OCMADDR14,
OCMADDR10,
OCMADDR17,
OCMADDR14,
OCMADDR10,
OCMADDR7,
OCMADDR3
O
Address signal output to the fl ash memory
AF21
OCMADDR0
O
Address signal output terminal Not used
AE22 to
AE26
OCMDATA12,
OCMDATA9
OCMDATA5 to
OCMDATA3
I/O
Two-way data bus with the fl ash memory
STR-DA3500ES
96
DSP BOARD IC5021 D790E002BZDH300 (DSP)
Pin No.
Pin Name
I/O
Description
A1
VSS
-
Ground terminal
A2
DVDD
-
Power supply terminal (+3.3V) (for IO)
A3
AFSX0
O
L/R sampling clock signal output to the D/A converter
A4
ACLKX0
O
Bit clock signal output to the D/A converter
A5
ACLKR0
I
Bit clock signal input from the digital audio interface receiver and HDMI receiver
A6
AXR0[14]/AXR2[1]
I
PCM audio signal input from the HDMI receiver
A7
VSS
-
Ground terminal
A8
AXR0[11]/AXR1[2]
I
PCM audio signal input from the A/D converter
A9
AXR0[9]/AXR1[4]/
SPI1_SIMO
I/O
Not used
A10
VSS
-
Ground terminal
A11
AXR0[6]/SPI1_ENA#
I/O
Not used
A12
AXR0[4]
I/O
Not used
A13, A14
AXR0[2], AXR0[0]
O
PCM audio signal output to the D/A converter
A15
DVDD
-
Power supply terminal (+3.3V) (for IO)
A16
VSS
-
Ground terminal
B1
DVDD
-
Power supply terminal (+3.3V) (for IO)
B2
UHPI_HBE[3]#
I
Not used
B3
AHCLKR0/AHCLKR1
I/O
Not used
B4
AFSR0
I
L/R sampling clock signal input from the digital audio interface receiver and HDMI receiver
B5 to B7
AXR0[15]/AXR2[0],
AXR0[13]/AXR1[0],
AXR0[13]/AXR1[0],
AXR0[12]/AXR1[1]
I
PCM audio signal input from the HDMI receiver
B8
AXR0[10]/AXR1[3]
I
PCM audio signal input from the digital audio interface receiver
B9
AXR0[8]/AXR1[5]/
SPI1_SOMI
I/O
Not used
B10
AXR0[7]/SPI1_CLK
I/O
Not used
B11
AXR0[5]/SPI1_SCS#
I/O
Not used
B12, B13
AXR0[3], AXR0[1]
O
PCM audio signal output to the D/A converter
B14
SPI0_SOMI
O
Serial data output to the system controller
B15
SPI0_SIMO
I
Serial data input from the system controller
B16
DVDD
-
Power supply terminal (+3.3V) (for IO)
C1
AMUTE0
O
Not used
C2
AHCLKX0/AHCLKX2
I
Master clock signal input from the digital audio interface receiver and HDMI receiver
C3
UHPI_HD[23]
I/O
Not used
C4 to C6
UHPI_HBE[2]# to
HPI_HBE[0]
I
Not used
C7
UHPI_HDS[2]#
I/O
Not used
C8
UHPI_HCS#
I/O
Not used
C9
UHPI_HAS#
I/O
Not used
C10
UHPI_HCNTL[1]
I/O
Not used
C11
AFSX2
I
Error signal input from the digital audio interface receiver, HDMI receiver and HDMI controller
C12
AFSR2
I
PCM audio data input from the digital audio interface receiver
C13
ACLKR2
I/O
Not used
C14
AHCLKR2
I/O
Not used
C15
SPI0_SCS#
I
Chip select signal input from the system controller
C16
SPI0_CLK
I
Serial data transfer clock signal input from the system controller
D1
AHCLKX1
I/O
Not used
D2
AMUTE1
O
Not used
D3
UHPI_HD[22]
I/O
Not used
D4, D5
DVDD
-
Power supply terminal (+3.3V) (for IO)
D6
UHPI_HRDY#
I
Not used
D7
UHPI_HDS[1]#
I/O
Not used
D8
UHPI_HRW
I
Not used
D9
UHPI_HCNTL[0]
I
Not used
D10
AMUTE2/HINT#
O
Not used
D11
ACLKX2
O
Interrupt signal output to the system controller
D12, D13
DVDD
-
Power supply terminal (+3.3V) (for IO)
D14
EM_WAIT
I
Not used
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