Sony STR-DA3500ES Service Manual ▷ View online
STR-DA3500ES
81
IC6502, 6503 SN74HC595ANS
– CIS Board –
IC802 TC7W53F (TE12R)
IC861 MAX3222IPWR
IC6504, 6505 NJM2533M (TE2)
2
SW1
3
VIN2
4
NC
1
VIN1
8 GND
7 VOUT
6 V+
5
BIAS
75
:
DRIVER
NC
1
2
3
4
5
6
7
8
9
10
16
15
14
13
12
11
SHIFT REGISTER
LATCH
PARALLEL DATA
OUTPUT
GND
VCC
LA
TCH
CLOCK
PARALLEL
DA
TA
OUTPUT
SERIAL
DA
TA
INPUT
OUTPUT
ENABLE
SHIFT
CLOCK
SERIAL
DA
TA
OUTPUT
RESET
QB
QC
QD
QE
QF
QG
QH
SQH
A
QA
IC6506 NJM2279M-TE2
SW 1 2
VIN 2 3
VIN 3 1
MUTE 2 4
VOUT 2 5
GND 2 6
GND 1 7
SW 2
13
VIN 1
12
V-
14
MUTE 1
11
VOUT 1
10
NC
9
V+
8
1
2
COMMON 1
INH 2
VEE 3
GND 4
CH 0
7
VCC
8
A
5
LOGIC
LEVEL
LEVEL
CONVERTER
C
OUT
IN
CH 1
6
C
OUT
IN
1
EN
2
C1+
3
V+
4
C1–
5
C2+
6
C2–
7
V–
8
DOUT2
9
RIN2
10
11
ROUT2
NC
14 NC
15 ROUT1
17 DOUT1
18 GND
19 VCC
20 PWRDOWN
16 RIN1
12 DIN2
13 DIN1
POWERDOWN
STR-DA3500ES
82
IC1402 SI-8008HFEK
– DCDC CON Board –
IC1401 SI-8050S-LF1101
OVER
CURRENT
PROTECTOR
LATCH
&
DRIVER
OVER HEAT
PROTECTOR
REGULATOR
+
–
–
+
–
–
RESET
VREF
COMPARATOR
ERROR AMP
OSC
1
VIN
2
SW OUT
3
GND
4
VOS
5
S.S
IN
1
SW
2
SS
5
ADJ
4
LATCH
&
DRIVER
ERROR AMP
COMPARATOR
OSCILLATOR
RESET
OVERCURRENT
PROTECTION
THERMAL
PROTECTION
REFERENCE
VOLTAGE
GND
3
ON/OFF
SOFT
START
PREG
+
+
+
–
–
IC1403 SI8008TM-TL
OVER
CURRENT
PROTECTOR
LATCH
&
DRIVER
OVER HEAT
PROTECTOR
REGULATOR
ON/OFF
SOFT
START
+
–
–
+
–
–
RESET
VREF
COMPARATOR
ERROR AMP
OSC
1
VIN
2
SW OUT
3
GND
4
ADJ
5
SOFT
ST
AR
T
STR-DA3500ES
83
• IC Pin Function Description
DIGITAL VIDEO BOARD IC3000 MB91F467RAPMC-GE1 (VIDEO SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
GND
-
Ground terminal
2 to 5
NO USE
-
Not used
6
STOP IN
I
AC off detection signal input terminal “L”: AC off
7
DAC CLOCK SEL
O
Clock control signal output to the frequency multiplier for D/A converter (for video section)
8, 9
EDID_MUX_A,
EDID_MUX_B
O
Input data selection signal output terminal
10
NO USE
-
Not used
11, 12
+3.3V
-
Power supply terminal (+3.3V)
13
GND
-
Ground terminal
14
C_1
-
External capacitor connection terminal for internal regulator
15
YAMAHA FLASH CE
O
Chip enable signal output terminal Not used
16, 17
NO USE
-
Not used
18
YAMAHA CE
O
Chip enable signal output to the OSD controller
19
SRAM CE
O
Chip enable signal output to the S-RAM
20
NO USE
-
Not used
21
YAMAHA RESET
O
Reset signal output to the fl ash memory and OSD controller “L”: reset
22
YAMAHA WAIT_N
I
Wait signal input from the OSD controller
23
YAMAHA READY_N
I
Ready signal input terminal Not used
24
NO USE
-
Not used
25
SRAM OE, UB, LB/
YAMAHA RD_N
O
Read enable signal output to the S-RAM and OSD controller
26
SRAM LB, WE
O
Lower-byte control signal and write enable signal output to the S-RAM
27
SRAM UB,WE/
YAMAHA WR_N
O
Upper-byte control signal and write enable signal output to the S-RAM, and write enable
signal output to the OSD controller
signal output to the OSD controller
28, 29
NO USE
-
Not used
30
TX_RST
O
Reset signal output to the HDMI transceiver “L”: reset
31
TX_5VPWR
O
Power supply on/off control signal output terminal for HDMI OUT connector “H”: power on
32
VDAC_RESET
O
Reset signal output to the D/A converter (for video section) “L”": reset
33, 34
NO USE
-
Not used
35
RX_RST
O
Reset signal output to the HDMI receiver “L”: reset
36
+3.3V
-
Power supply terminal (+3.3V)
37
C_2
-
External capacitor connection terminal for internal regulator
38
GND
-
Ground terminal
39
X0
I
Main system clock input terminal (4 MHz)
40
X1
O
Main system clock output terminal (4 MHz)
41
GND
-
Ground terminal
42
X0A
I
Sub system clock input terminal Not used
43
X1A
O
Sub system clock output terminal Not used
44
+3.3V
-
Power supply terminal (+3.3V)
45
GND
-
Ground terminal
46 to 53
SRAM IO0 to SRAM
IO7
I/O
Two-way data bus with the S-RAM
54 to 56
SRAM IO8/YAMAHA D0
to SRAM IO10/
YAMAHA D2
I/O
Two-way data bus with the S-RAM and OSD controller
57
+3.3V
-
Power supply terminal (+3.3V)
58
GND
-
Ground terminal
59 to 63
SRAM IO11/YAMAHA
D3 to SRAM IO15/
YAMAHA D7
I/O
Two-way data bus with the S-RAM and OSD controller
64
YAMAHA PS0
O
Address signal output to the OSD controller
65, 66
SRAM A0/YAMAHA
PS1, SRAM A1/
YAMAHA PS2
O
Address signal output to the OSD controller and S-RAM
67 to 72
SRAM A2 to SRAM A7
O
Address signal output to the S-RAM
73
+3.3V
-
Power supply terminal (+3.3V)
74
GND
-
Ground terminal
75 to 83
SRAM A8 to SRAM A16
O
Address signal output to the S-RAM
STR-DA3500ES
84
Pin No.
Pin Name
I/O
Description
84 to 87
NO USE
-
Not used
88
GND
-
Ground terminal
89
+3.3V
-
Power supply terminal (+3.3V)
90, 91
NO USE
-
Not used
92
NON_LPCM
O
Non-LPCM setting signal output terminal “L”: LPCM
93
1444_HPD
O
Hot plug detection control signal output to the HDMI input selector
94
1444_OEB
O
Output enable signal output to the HDMI input selector
95, 96
+5V_SELA, +5V_SELB
O
HDMI +5V power input selection signal output terminal
97
NO USE
-
Not used
98
AUDIO MUTE
REQ
O
Audio muting signal output terminal
99 to 101
1444_SELA to
1444_SELC
O
HDMI input selection signal output to the HDMI input selector
102
HPD_IN1
O
Hot plug detection control signal output to the HDMI VIDEO 1 IN connector
103 to 113
NO USE
-
Not used
114
GND
-
Ground terminal
115, 116
+3.3V
-
Power supply terminal (+3.3V)
117
UC3V_SDA
I/O
I2C data bus with the D/A converter (for video section), EEPROM, HDMI receiver and HDMI
transceiver
transceiver
118
UC3V_SCL
O
I2C clock signal output to the D/A converter (for video section), EEPROM, HDMI receiver
and HDMI transceiver
and HDMI transceiver
119
YAMAHA_INT_N
I
Interrupt signal input from the OSD controller
120
NO USE
-
Not used
121
RX_INT
I
Interrupt signal input from the HDMI receiver
122
NO USE
-
Not used
123
TX_INT
I
Interrupt signal input from the HDMI transceiver
124
NO USE
-
Not used
125
Faroudjia Power
DETECT
I
Power detection signal input from the video processor
126
Faroudjia UCOM
RESET
O
Reset signal output to the fl ash memory and video processor “L”: reset
127
MD3
-
Mode setting terminal Fixed at “L” in this set
128
MD2
I
Mode setting signal input from the system controller
129, 130
MD1, MD0
-
Mode setting terminal Fixed at “L” in this set
131
INITX
I
Reset signal input from the system controller “L”: reset
132
GND
-
Ground terminal
133
+5V
-
Power supply terminal (+3.3V)
134
Flash Update RX
I
Serial data input terminal
135
Flash Update TX
O
Serial data output terminal
136
ENDFLAG
O
End fl ag output to the system controller
137
MAIN UCOM
UART RX
I
Serial data input from the system controller
138
MAIN UCOM
UART TX
O
Serial data output to the system controller
139
MAIN UCOM
UART BUSY
I
Busy signal input from the system controller
140
Faroudjia UCOM
UART RX
I
Serial data input from the video processor
141
Faroudjia UCOM
UART TX
O
Serial data output to the video processor
142
Faroudjia UCOM
BUSY
I
Busy signal input from the video processor
143 to 145
NO USE
-
Not used
146
GND
-
Ground terminal
147
+5V
-
Power supply terminal (+3.3V)
148 to 160
NO USE
-
Not used
161
GND
-
Ground terminal
162
+5V
-
Power supply terminal (+3.3V)
163 to 167
NO USE
-
Not used
168
V.SYNC_DET
I
Vertical sync signal input from the HDMI receiver
169 to 175
NO USE
-
Not used
176
+5V
-
Power supply terminal (+3.3V)
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