DOWNLOAD Sony SCD-XA9000ES Service Manual ↓ Size: 10.59 MB | Pages: 123 in PDF or view online for FREE

Model
SCD-XA9000ES
Pages
123
Size
10.59 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio
File
scd-xa9000es.pdf
Date

Sony SCD-XA9000ES Service Manual ▷ View online

SCD-XA9000ES
25
25
CLV Jitter Check (CD only)
Connection:
Checking Method:
Under the condition of RF level check mode in step 3, connect the
oscilloscope to the TP516 (RFCK) (CH1), TP517 (WFCK) (CH2),
and the TP808 (DGND) (GND) on the MAIN board to check that
the value A of the waveform satisfies the specification.
Note:
 Take care not to leave the test disc in the set.
Specified Value:
Disc
A
PATD-012 or
35 
µsec or less
YEDS-18
A
CLV jitter waveform
MAIN board
TP516 (RFCK)
TP517(WFCK)
TP808 (DGND)
+
+
oscilloscope
(CH2)
(CH1)
RF Level Check
Connection:
Checking Method:
1. Under the condition of traverse waveform check mode in step
4, press the 
[        AMS        ]
 dial.
2. Connect an oscilloscope to the TP703 (RFAC) and TP704
(AGND) on the MAIN board.
3. After “WAIT” is displayed, the RF waveform check mode will
become active and “PLAY 5th TRACK”  (for the SACD, “RF
MODE ON”) will be displayed, and the 5th music on the disc
will be played.
4. Check that the RF waveform is clear and the level satisfies the
specification.
5. Press the 
[        AMS        ]
 dial (for the SACD, “RF JITTER
(5th)” will be displayed, and further press the AMS dial), and
“OUTSIDE TRACK” will be displayed and the outward track
of the disc will be played.
6. Check that the RF waveform is clear and the level satisfies the
specification.
7. Press the 
[        AMS        ]
 dial, and “INSIDE TRACK” will be
displayed and the inward track of the disc will be played.
8. Check that the RF waveform is clear and the level satisfies the
specification.
9. After checking, press the 
[        AMS        ]
 dial, and the test is
over when “BU MEASURE” is displayed.
10. Press the 
[OPEN/CLOSE    ]
 button to open the tray, and re-
move the test disc.
11. Using each type of disc, repeat from step 1 of S curve wave-
form check up to step 10 of RF level check.
12. When the check is over, press the 
[POWER]
 button to turn the
power off.
Note:
 Take care not to leave the test disc in the set.
Specified Value:
Disc
A
SATD-S5 or
SATD-S4
PATD-012 or
0.9 to 1.4 Vp-p
YEDS-18
Note:
 Clear RF waveform refers to the waveform where 
◊ shapes should
be distinctively observed in the center.
Checking and Connecting Location : MAIN Board
MAIN board
TP703 (RFAC)
TP704 (AGND)
+
oscilloscope
VOLT/DIV: 200 mV
TIME/DIV: 500 ns
RF signal waveform
A
l
L
l
L
l
L
l
L
A
Traverse Check
Connection:
Checking Method:
1. Under the condition of S curve waveform check mode in step
5, press the 
[        AMS        ]
 dial.
2. After “WAIT” is displayed, the traverse waveform check mode
will become active and “TRV MODE ON” will be displayed.
3. Connect an oscilloscope to the TP513 (TE) and TP504 (AVC)
on the MAIN board.
4. Check that the level A and B of waveform on the oscillo-
scope satisfy the specification.
Specified Value:
Disc
A
B
SATD-S5 or
SATD-S4
PATD-012 or
0.9 to 1.4 Vp-p
–0.1 to +0.1V
YEDS-18
Checking and Connecting Location : MAIN Board
MAIN board
TP513 (TE)
TP504 (AVC)
+
oscilloscope
A
B
VC
Center fo the waveform
Traverse waveform
l
L
TP808
(DGND)
TP704
(AGND)
TP703
(RFAC)
TP517
(WFCK)
TP516
(RFCK)
TP504
(AVC)
TP513
(TE)
TP506
(FE)
IC801
IC802
IC701
– MAIN Board (Component Side) –
IC504
IC509
Checking and Connecting Location:
4-7. i.LINK SIGNAL OPERATION CHECK
Connect the set to a unit equipped with the i.LINK terminal to
check if the bus reset occurs correctly. By this operation, a loose
connection of the connector or a disconnection of the i.LINK cable
can be checked.
Note:
 Do not perform the operation other than the specified operation in
the following i.LINK test mode, as the set otherwise may not oper-
ate normally.
Checking Method:
1. Press the 
[POWER]
 button to turn the power on, and rotate the
[       AMS       ]
 dial to select the “i.LINK” function (i.LINK
LED (blue) lights up). Then, with the 
[TIME/TEXT]
  button
kept pressed, press the 
[OPEN/CLOSE    ]
 button, 
[    ]
 button,
and 
[    ]
 button in this order, so that the i.LINK test mode is
activated and “<< [BACK] >>” is displayed on the fluorescent
display tube.
2. With “<< [BACK] >>” displayed on the fluorescent display
tube, rotate the 
[        AMS        ]
 dial clockwise to advance the
display by five steps, so that “B.Rst. [000]” is displayed. This
counter increments by one or several counts each time the bus
reset occurs.
3. Turn on the power of the unit equipped with the i.LINK termi-
nal, and connect the set to the unit equipped with the i.LINK
terminal using the i.LINK cable to check if the bus reset oc-
curs correctly. If the bus reset does not occur, or if the bus
reset occurs continuously, the i.LINK cable will be discon-
nected or the connector connection will be loose.
Note:
 The bus reset may not occur unless the power of the unit equipped
with the i.LINK terminal is turned on when it is connected.
4. With the set connected to the unit equipped with the i.LINK
terminal using the i.LINK cable, move the i.LINK cable to
check if the bus reset occurs. If the bus reset occurs though the
i.LINK cable is not removed, the i.LINK cable will be discon-
nected or the connector connection will be loose.
5.  Press the 
[POWER]
 button to turn the power off, or rotate the
[        AMS        ]
 dial counterclockwise so as to display “<<
[BACK] >>”, and then press the 
[MENU]
 button, so that the
i.LINK test mode is deactivated.
l
L
l
L
N
x
l
L
A
Ver 1.1
SCD-XA9000ES
26
26
• Signal Path
: SACD PLAY
: CD PLAY (ANALOG OUT)
: CD PLAY (DIGITAL OUT)
A
B
C
F
E
H
G
1
63
3
4
5
6
18
17
12
11
10
9
22
24
20
12
11
5
6
2
9
3
25
8
9
24
23
20
LASER
DIODE
(CD)
48
47
46
41
40
50
64
66
67
65
71
17
80
79
10
14
24
22
19
15
13
8
7
6
5
4
3
77
76
63
2
25
39
39
40
38
43
DETECTOR
OPTICAL PICK-UP
BLOCK
(KHM-230AAA)
33
30
26
31
(FOCUS)
(TRACKING)
2-AXIS
DEVICE
VC
(+2.5V)
MODULE
CIRCUIT B+
FOCUS
COIL
DRIVE
SLED
MOTOR
DRIVE
SPINDLE
MOTOR
DRIVE
STANDBY1
STANDBY2
MUTE2
TRACKING
COIL
DRIVE
M
M
14
13
FD+
FD–
TD+
TD–
13
29
32
34
RF
A
B
C
D
E
F
G
H
DVDRFP
A2
B2
C2
D2
CD_E
CD_F
A
B
C
D
57
62
61
59
60
53
52
54
55
20
27
SDEN
SDEN
SDATA
DATA_RF
SCLK
CLK_RF
TE
TE
FE
FE
PI
PI
RFAC
MIRR
MIRR
CDLD
CDPD
VC
CD_LD
CD_PD
A+5V
M3
(SPINDLE)
M2
(SLED)
S1
(LIMIT)
RFAC
DOUT
TE
RFDC
FFDR
SRDR
TFDR
SFDR
TRDR
FRDR
MIRR
SRDR
TFDR
SFDR
TRDR
SD+
D+3.3V
SD– 
FFDR
FRDR
FJMP1
FJMP2
TFDR
TRDR
SFDR
SP_ERR
SRDR
17
FOCUS/TRACKING COIL DRIVE,
SLED MOTOR DRIVE
IC502
ATOP
ATON
AIP
AIN
FNP
FNN
DIP
DIN
26
LDON
LDON
16
15
14
13
CD_A
CD_B
CD_C
CD_D
6
5
LOADING
MOTOR
DRIVE
MUTE1
M
2
LOAD+
LOAD–
VMOD
22
SACD/CD RF AMP,
FOCUS/TRACKING ERROR AMP
IC001
21
23
LASER
DIODE
(SACD)
DVDLD
DVDPD
DVD_LD
VC
DVD_PD
RFSIN
VMOD
SPINDLE/LOADING
MOTOR DRIVE
IC512
M1
(LOADING)
17
18
27
26
SSTP
LIM_SW
MUTE_2D
SP_ON
MUTE_LOAD
SPDA
SPIN
LOAD_IN
LOAD_OUT
+1.65V
AVC
+1.65V
A+3.3V
RFAC
SE
FE
COAXIAL
OPTICAL
DIGITAL (CD)
OUT
J391
MDAT
BCLK
LRCK
DOON
LRCK
768_CD
GSCOR
EXCK
SBSO
SBSO
WFCK
WFCK
C2PO
C2PO
21
DFCT
DFCT
LOCK
FOK
COUT
SCOR
GFS
SCLK
SENS
CLOK
XLAT
DATA
MUTE_CD
SQCK
SQSO
MD2
LOCK
FOK
COUT
SCOR
GFS
SCLK
SENS
CLOK
XLAT
DATA
MUTE
SQCK
SQSO
MD2
XRST_CD
VMOD, SDEN,
LIM SW, XRST_CD
MIRR, DATA_RF, CLK_RF, LDON,
SP_ON, LOAD IN, LOAD OUT,
MUTE LOAD, MUTE_2D, SP_ERR
TE, FE, PI,
FJMP1, FJMP2, SPDA
MDP, SPIN
MDP
MDP
DOUT
PCMD
BCK
XTAI
WDCK
EXCK
XRST
DIGITAL SERVO PROCESSOR,
DIGITAL SIGNAL PROCESSOR,
DIGITAL FILTER
IC509
AUTOMATIC POWER
CONTROL (FOR SACD)
Q001
AUTOMATIC POWER
CONTROL (FOR CD)
Q003
B+ SWITCH
Q002, 005
COMPARATOR
IC081 (1/2)
COMPARATOR
IC081 (2/2)
VC BUFFER
IC004 (1/2)
21
OPTICAL
TRANSCEIVER
IC442
DIGITAL OUT
ON/OFF SWITCH
IC810
(Page 27)
(Page 27)
V
(Page 29)
X
(Page 31)
(Page 28)
(Page 27)
(Page 28)
(Page 28)
(Page 28)
WAVE
SHAPER
IC441
PI ERROR
AMP
IC004 (2/2)
T441
SECTION  5
DIAGRAMS
5-1.
BLOCK  DIAGRAM  – RF/SERVO Section –
SCD-XA9000ES
27
27
CENTER VOLTAGE
GENERATOR
IC503
A
I
J
E
K
B
M
L
N
• Signal Path
: SACD PLAY  
17
33
18
34
76
94
78
95
35
137
135
146
17
164
18
19
20
21
147
148
151
158
160
163
107
109
155
MA0 – MA9
5, 7, 9 – 14
48
49
46
53
26
166
165
167
164
167
169
170
93
169 – 176
SD0 – 7
123
9
10
2
3
4
6
7
WCK
XRST
87 IANCO
XRST_DSD
256FS
141
145
144
143
DCLK
XRAS
XCAS
XWE
PHREFI
BCKAI
35
17
16
15
117
RFAC
16Mbit
D-RAM
IC706
I/O0 – I/O15
A0 – A9
WE
OE
RAS
UCAS
LCAS
MDB0 – MDBF
D0 – D7
A0 – A7
XMWR
XMOE
XRAS
XCAS
RFIN
D0 – D7
A0 – A7
HDB0 – HDB7
XHWR
XHRD
XDRQ
XHAC
HDB8
MA11
168 SDEF
XSRQ
126
127
WARFI
XSAK
XSHD
SDCK
A0 – 11
A0 – 11
DQ0 – 7
16Mbit D-RAM
IC808
CLK
RAS
CAS
WE
DQ0 – 7
142
DCKE
34 CKE
2 – 5, 7 – 10,
41 – 44, 46 – 49
44, 41, 39, 35,
32, 30, 27, 24
IOUT0 – IOUT5
78, 79, 81,
82, 84, 85
172 – 176,
1, 2, 4
79 – 80,
82 – 87, 89, 91
21 – 24,
27 – 32
162–159,157–154
152,151,149,148
21 – 24,27 – 32
20 , 19
CLOCK
GENERATOR
IC811
66 – 69, 71, 73 – 75,
96, 97, 99, 101, 102,
104 – 106
88 IFULL
89 IEMPTY
91 IFRM
92 IOUTE
93 IBCK
ANCIO
IFULL
IEMPTY
IFRM
IOUTE
IBCK
XRST_DVD
XHRD
XHWR
XCS1882
XINIT0
XINIT1
XRST
XRD
XWR
XCS
XINT0
XINT1
GSCOR 
EXCK
SBSO
WFCK
C2PO
BCLK
MDAT
LRCK
MDP
SPIN
GFS_V
JIT
APDO
MDIN2
SPO
GSCOR
EXCK
WFCK
SBIN
C2PO
BCLK
MDAT
LRCK
145
DFCT
DFCT
150
SCOR
768_CD
SCOR
GFS
APEO
SACD DECODER
IC701
LEVEL
SHIFT
IC812
LEVEL
SHIFT
IC813
XTAL
XTL2
XTL1
SMUTE
XMSLAT
MSCK
MSDATI
MSDATO
MSREADY
MUTE_DSD
XLAT_DSD
SCK_DSD
SOUT_DSD
SIN_DSD
RDY_DSD
115
TEST1
SAMBA_TEST
74
75
72
73
70
SI
SO
SCLK
XCS
XRST
80
PHRI
81
DSAL
WAVRB
83 DLI
64
DSAR
84
DRI
66
DSAC
85
DCI
69
DSASW
86
DLFEI
71
DSALS
87
DLSI
74
DSARS
88
DRSI
76
DRO
DLSO
DRSO
DCO
DLFEO
DLO
SDATAR
SDATALS
SDATARS
SDATAC
SDATASW
SDATAL
38
37
32
31
35
34
61
59
BCKAI
SOUT_DSD
SIN_DY
SCK_DSD
XCS_DY
RST_DY
128FS
64FS
11
MCKI
768FS
768FS
768_DVD
768_CD
DSD DECODER
IC801
DSD
DIGITAL
SIGNAL
PROCESSOR
IC802
11 – 18
9 – 2
4
3
2
16
5
15
17
18
139 – 136
134 – 131
2 ,3 ,5 ,6
8 ,9 ,11 ,12
12
13
15
14
RAS
CS
CKE
CLK
17
18
34
35
D0 – D15
DQ0 – DQ15
A0 – A11
16Mbit SD-RAM
IC803
RAS
CS
CKE
CLK
A0 – A11
11
CAS
16 CAS
10
WE
68
CLK512
15 WE
1 – 5, 7, 8, 90 – 95,
97, 98, 100
2, 3, 5, 6, 8, 9, 11, 12, 39,
40, 42, 43, 45, 46, 48, 49
17 – 22,
24 – 29
19 – 24,
27 – 32
LEVEL
SHIFT
IC814
(Page 26)
(Page 28)
(Page 28)
(Page 28)
(Page 26)
(Page 26)
(Page 28)
Y
(Page 31)
(Page 28)
(Page 29)
W
(Page 29)
DVC
A+3.3V
DRVC +2.5V
D+5V
ADDRESS BUS
DATA BUS
DATA BUS
LEVEL SHIFT
IC708
COMPARATOR
IC703 (1/2)
VC BUFFER
IC703 (2/2)
IOUT0 –
IOUT5
CLOCK
GENERATOR
IC804
5-2.
BLOCK  DIAGRAM  – MAIN Section (1/2) –
SCD-XA9000ES
28
28
J
I
H
M
Q
P
F
C
G
K
8
43
72
35
1
6
67
3
66
65
9
75
74
71
34
79
78
38
85
84
12
22
23
11
10
97
62
99
76
5
60
51
52
53
54
56
49
50
47
27
73
37
33
26
83
77
25
100
59
64
58
30
31
36
29
6
5
40
41
89 – 96
14 – 21
A0 – A7
D0 – D7
DATA BUS
ADDRESS BUS
DATA BUS
ADDRESS BUS
XTAL
EXTAL
X901
20MHz
7
36
26
33
31
22
24
11
10
9
35
32
12 – 16, 19 – 22
A
D0 – D7
RST_DVD
FJMP1
FJMP2
SPDA
TE
FE
PI
TE
FE
PI
MD2
SENS
LOCK
FOK
GFS
DATA
XLAT
COUT
SCLK
CLOK
MUTE_CD
SQCK
SQSO
SCOR
SQCK_CD
SQSO
SCOR_CD
63
DOON
DOON
DATA_RF
CLK_RF
MIRR
LDON
SP_ERR
SP_ON
SP_ON
MUTE_LOAD
MUTE_LOAD
46
45
LOAD_IN
LOAD_IN
LOAD_OUT
LOAD_OUT
JIT
JITTER
GFS_V
GFS_DVD
44
APDO
APDO
IN_SW
OUT_SW
FCS_JMP_1
FCS_JMP_2
SPDA
DOCTRL
SENS_CD
LOCK_CD
FOK_CD
GFS_CD
DATA_CD
XLAT_CD
COUT_CD
SCLK_CD
CLOK_CD
MUTE_CD
DATA_RF
CLK_RF
MIRR_RF
LDON
SP_ERR
4
MUTE_2D
MUTE_2D
XRD
XWR
XCS_DVD
INIT0_DVD
INIT1_DVD
XCS_IO
XDIS_IO
RST 
INIT_DF
LATCH_DF_B
SWGUP
MULTI
MODE_SACD
AMUT_MCH
BUSY_DP
SIN_DP
SOUT_DP
 SCK_DP
REQ-DP
SOUT_DSD
SCK_DSD
XLAT_DSD
RDY_DSD
EEPSIO
EEPSCL
48
SIN_DSD
XHRD
XHRD, XHWR, XCS1882,
XINIT0, XINIT1, XRST_DVD
XHWR
XCS1882
XINIT0
XINIT1
INIT_DF
98
LATCH_DF
LAT_DF_A
DATA_DF
DATA_DF, CLK_DF, INIT_DF,
LAT_DF_A, LAT_DF_B,
MODE_SACD, MULTI
61
MLS_RST
82
MLS_OSC
CLK_DF
MLS_RST
MLS_OSC
MLS_SIO
MLS_SIO, MLS_SCK,
MLS_RST, MLS_OSC
MLS_SCK
LAT_DF_B
SWGUP
SWGUP, AMUTE,
AMUT_MCH
MULTI
MODE_SACD
AMUT_MCH
XFBSY
XFBSY, SIO, SOO,
SCO, XIFCS, XFRRST
SIO
SOO
SCO
XIFCS
SOUT_DSD
SCK_DSD
XLAT_DSD
SIN_DSD
SIN_DSD, SIN_DY, SOUT_DSD,
SCK_DSD, XLAT_DSD, RDY_DSD,
MUTE_DSD, XCS_DY, RST_DY,
XRST_DSD, SAMBA_TEST
SIN_DY
RDY_DSD
28
MUTE_DSD
MUTE_DSD
57
XCS_DY
XCS_DY
2
RST_DY
RST_DY
EEPROM
IC903
SDA
SCL
D0 – D7
A0 – A7
XRST_DVD
RST
XWR
XRD
XCS
RST_DP
1
SI_SELRKSW
37
AMUTE
ISBTEST
SAMBA_TEST
25
RST_DSD
XRST_DSD
XFRRST
AMUTE
VMOD
RST_CD
SDEN
VMOD
XRST_CD
SDEN
44
LIM_SW
LIM_SW
I/O EXPANDER
IC904
CPU
IC901
D+3.3V
S001
(LOADING IN)
OFF
r
IN
OFF
r
OUT
S002
(LOADING OUT)
RESET
SIGNAL GENERATOR
IC905
(Page 26)
(Page 26)
(Page 26)
L
(Page 27)
Z
(Page 31)
(Page 27)
(Page 27)
(Page 27)
(Page 26)
(Page 27)
(Page 32)
(Page 29)
S
DATA_DF, CLK_DF, INIT_DF,
LAT_DF_A, LAT_DF_B, MULTI
(Page 30)
O
(Page 30)
LEVEL
SHIFT
IC906 (1/2)
LEVEL SHIFT
IC906 (2/2)
DATA SELECT
IC902
5-3.
BLOCK  DIAGRAM  – MAIN Section (2/2) –
Page of 123
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