Sony SCD-XA9000ES Service Manual ▷ View online
SCD-XA9000ES
41
41
FL807
C856
R851
R835
R836
R837
R838
R840
R841
R842
R826
R850
R821
R822
R848
R849
C861
C857
C855
R1014
R1019
C860
C858
FB720
R866
C817
C818
C808
R829
C810
R831
R827
C807
R828
R839
R800
C838
C839
IC813
IC814
C813
R847
IC812
C811
C819
C812
C843
C854
R1015
FL811
C941
C865
C867
C866
R852
R834
R833
R832
R809
C870
C815
C809
C871
C800
FL813
FB717
C848
C841
FL812
C795
C797
C796
FB719
C803
C802
D904
FL810
FB716
C837
C849
C804
R830
R882
R883
R884
R885
R886
R887
R888
R889
C842
IC808
R870
FB718
C840
IC702
IC801
TP808
0.01
0
0
0
0
0
0
0
0
22
22
22
22
22
22
0.01
0.01
0.01
0
0
0.01
100
6.3V
220
0.01
0.01
100p
100
0.01
33k
100
0.01
4.7k
4.7k
4.7k
0.01
0.01
SN74LV245APWR
SN74AHCT1G08DCKR
0.01
22
SN74LV245APWR
0.01
0.01
0.01
0.01
0.01
22
1
0.01
0.01
0.01
0
0
0
0
100
0.022
0.01
10
10V
0.01
0.01
0.01
10
10V
100
6.3V
220
4V
1
0.01
10
10V
1SS367
0.01
0.01
0.01
4.7k
10k
10k
10k
10k
10k
10k
10k
10k
0.01
MSM56V16160F-10T
10k
10
10V
TA48M025F
CXD2753R
(DGND)
D1
D2
D3
D4
D5
D6
D7
D8
D9
E1
E2
E3
E4
E5
F1
F2
DSD_BUS
DGND
AGND
D3V
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
XSHD
SDCK
XSHD
XSAK
SDEF
XDCK
AV0
AV1
AV2
AV3
AV4
AV5
AV6
AV7
SDEF
XSAK
XSAK
SDEF
XSHD
SDCK
AV0
AV1
AV2
AV3
AV4
AV5
AV6
AV7
XSRQ
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SCAS
SRAS
SWE
DCLK
DCKE
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
S
A
4
S
A
5
S
A
6
S
A
7
S
A
8
S
A
9
D
C
L
K
D
C
K
E
128FS
64FS
D
Q
0
D
Q
1
D
Q
2
D
Q
3
D
Q
4
D
Q
5
D
Q
6
D
Q
7
S
W
E
S
C
A
S
S
R
A
S
S
A
1
1
S
A
1
0
S
A
0
S
A
1
S
A
2
S
A
3
P
C
K
O
R
F_
A
C
W
A
V
R
B
IOUT0
IOUT1
IOUT2
IOUT3
IOUT4
IOUT5
DSAL
DSAR
DSAC
DSASW
DSASL
DSASR
M
U
T
E
_
D
S
D
X
R
S
T
_
D
S
D
R
D
Y
_
D
S
D
S
IN
_
D
S
D
S
O
U
T
_
D
S
D
S
C
K
_D
S
D
X
L
A
T
_
D
S
D
IFULL
ANCIO
SD5V
IB
C
K
IO
U
T
E
IF
R
M
IE
M
P
T
Y
D
Q
6
D
Q
7
VDD
VDD
VSS
VSS
DQ0
DQ1
VSSQ
DQ2
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
LDQM
WE
CAS
RAS
CS
A10/AP
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
NC
CKE
CLK
UDQM
NC/RFU
DQ8
DQ9
VSSQ
DQ10
DQ11
VDDQ
DQ12
DQ13
VSSQ
DQ14
DQ15
A11-BA
VDDQ
IN
G
O
U
T
(4/7)
LEVEL SHIFT
LEVEL SHIFT
LEVEL SHIFT
16Mbit D-RAM
+2.5V REGULATOR
DSD DECODER
5-16. SCHEMATIC DIAGRAM – MAIN Board (4/7) –
•
See page 65 for Waveforms.
(Page 39)
(Page 43)
(Page 42)
(Page 44)
SCD-XA9000ES
42
42
CN710
CN702
CN701
R983
R1072
R982
R918
C951
R854
R853
R855
C846
FL808
FB727
R862
R863
R864
C954
R868
R861
C847
C953
R858
R859
C851
C852
C850
R860
FB804
R813
R814
R815
R816
R817
R818
C822
C820
C824
R811
C844
C845
FL809
FB722
C826
C825
C827
C828
C832
FB723
FL905
C830
IC803
C829
D905
IC815
R865
R867
C882
FB762
C883
C823
C831
C821
R810
R1054
R1055
R1056
R1057
R1058
R1059
R1060
R1061
R1062
R1063
R1064
R1065
R1066
R1067
R1068
R1069
R1070
R1031
R1032
R1033
R1034
R1035
R1036
R1037
R1038
R1039
R1040
R1041
R1042
R1043
R1044
R1045
R1046
R1047
R1048
R1049
R1050
R1051
R1052
R1053
FB801
FB802
FB803
IC804
IC811
IC802
25P
19P
19P
22
0
22
2.2
0.1
220
220
220
100
6.3V
100
10k
100
100p
47
100
0.1
0.1
680
680
L801
1
µH
L802
1
µH
L803
1
µH
22p
22p
22p
220
22
22
22
22
22
22
0.1
0.1
0.1
0
0.1
220
4V
0.1
0.1
0.1
0.1
10
10V
0.1
MSM56V16160F-10T
0.1
1SS367
SN74AHC1GU04DCKR
100k
220
0.1
0.001
0.1
0.1
0.01
100
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SN74LV86APWR
SN74LVU04APWR
CXD9722TQ
D1
D2
D3
D4
D5
D6
D7
D8
D9
G1
H1
H2
H3
CD_BUS
BCLK
DOUT
LRCK
MULTI
CLK_DF
DATA_DF
MDAT
INIT_DF
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
1
0
D
1
1
D
1
2
D
1
3
D
1
4
D
1
5
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
1
0
A
1
1
W
E
C
A
S
R
A
S
C
S
C
L
K
C
K
E
A
0
A
1
A
2
A
3
A4
A5
A6
A7
A
8
A
9
A
1
0
A
1
1
D0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D8
D9
D10
D11
D12
D13
D14
W
E
C
A
S
R
A
S
C
S
C
L
K
C
K
E
D15
DSAL
DSAR
DSAC
DSASW
DSASL
DSASR
S
IN
_
D
Y
S
C
K
_
D
S
D
X
C
S
_
D
Y
S
O
U
T
_
D
S
D
R
S
T
_
D
Y
64FS
128FS
MODE_SACD
64FS
DSLO
DSRO
DSCO
DSLFO
DSLSO
DSRSO
SWGUP
AMUT_MCH
LAT_DF_A
LAT_DF_B
AMUTE
128FS
MLS_OSC
MLS_RST
MLS_SCK
IFULL
IEMPTY
ANCIO
IOUT1
IOUT2
IOUT3
IOUT4
IOUT5
IOUTE
IFRM
IBCK
MLS_SIO
IOUT0
DSLO
DSRO
DSCO
DSLFO
DSLSO
DSRSO
7
6
8
_
C
D
7
6
8
_
D
V
D
D
O
U
T
AMUTZ
INIT
SDATAC
GND
GND
GND
GND
MULTI
DFGND
DFGND
SDATASW
SWGAINUP
GND
GND
CDBCK
CDLRCK
SDATAR
SDATAL
GND
GND
GND
GND
SDATARS
SDATALS
GND
CDDATA
GND
CDDATA-SUB
GND
CDDATASL
IFULL
ANCIO
IOUT1
IOUT2
IOUT3
IOUT4
IOUT5
IOUTE
IFRM
IBCK
DOUT
MLS_SIO
MLS_RST
MLS_OSC
DGND
DGND
DGND
DGND
DGND
DGND
DGND
(OSC)
(RST)
(SCL)
(SDA)
(REQO)
(DTSPD)
(ANCII)
(DT1I)
(DT2I)
(DT3I)
(DT4I)
(DT5I)
(DT6I)
(VALIN)
(FPRI)
(SACKI)
(IEC958)
MLS_SCK
IEMPTY
NC
IOUT0
(5/7)
+3.3V-D
MODE(SA/CD)
256FS
128FS
DATA.DAC
SHIFT.DAC
LATCH.DAC
64FS
GENERATOR
CLOCK
GENERATOR
CLOCK
16Mbit SD-RAM
CLOCK
BUFFER
DSD DIGITAL
SIGNAL PROCESSOR
5-17. SCHEMATIC DIAGRAM – MAIN Board (5/7) –
•
See page 65 for Waveforms.
(Page 41)
(Page 43)
(Page 44)
(Page 39)
(Page 48)
(Page 48)
(Page 57)
SCD-XA9000ES
43
43
FL908
C945
C946
R
94
0
R
9
4
1
C
9
1
0
C
90
5
R
9
42
R
10
2
0
R
97
1
R
9
70
R
10
2
8
R
1
0
30
R1021
R958
C925
R988
R917
R916
TP701
C909
C915
C908
C746
C903
C904
R991
R992
R1023
R915
R824
R965
R920
R921
R981
R998
R919
IC903
C916
R
9
0
6
R
9
51
R
9
07
R
9
05
R
9
96
R
9
04
R
9
0
3
R
9
0
1
R912
R913
R946
C902
C901
FL901
C906
R804
R902
R932
R957
R955
IC905
R964
C921
R963
R949
R948
R947
R1003
R1002
R980
R910
R956
R959
R962
FB721
R960
R961
C923
C920
C924
R
1
02
2
R
10
29
R
9
73
R
9
43
TP902
R978
IC901
IC902
X901
R929
R926
R925
0.1
0.1
1
0
0
1
0
0
0
.01
0
.01
1
00
10
k
1
00
1
0
k
10
0
1
0
0
1k
10k
0.1
1k
1k
1k
XX
100p
100p
0.01
0.22
10
10V
0.01
0
0
0
100
0
10k
100
100
10k
0
22
BR24C02F-WE2
0.01
2
2
1
k
2
2
2
2
0
2
2
22
22
10k
10k
10k
0.01
10
10V
0.01
10k
10k
22
22
22
M51957BFP-600C
1k
0.01
1k
6.8k
6.8k
0
10k
10k
2.2k
0
10k
10k
10k
10k
1k
1
0.01
0.01
8
.2k
8
.2
k
0
1
00
10k
CXP973064-241R
TC7WH157FU
20MHz
100
100
100
E
1
E
2
E
3
E4
E5
G
1
I2
I3
I4
I5
I6
I7
I8
I9
SPC970_BUS
ANALOG_BUS
PARA_BUS
A3V
A0
A1
A2
A3
A4
A5
A6
A7
D0
D1
D2
D3
D4
D5
D6
D7
CLK_RF
DA
T
A_RF
IN_SW
OUT_SW
COUT
SQSO
TXD
RXD
XCS_IO
MD2
GFS_V
JIT
LOCK
FOK
SCLK
GFS
XCS1882
XHRD
XHWR
SENS
FJMP1
FJMP2
PI
APDO
SPDA
MUTE_2D
SP_ON
MUTE_CD
MIRR
SQCK
DA
T
A
XLA
T
SCOR
SCK_DSD
SOUT_DSD
XLA
T_DSD
INIT_DF
MUTE_LOAD
XINT0
XINT1
RDY_DSD
LOAD_IN
LOAD_OUT
FE
SP_ERR
TE
SIN_DSD
CLOK
LDON
SWGUP
RST_DY
MUTE_DSD
LAT_DF_B
LA
T_DF_A
BUSY_DP
SIN_DP
REQ_DP
XCS_DY
SOUT_DP
SCK_DP
MLS_OSC
MLS_SCK
MLS_SIO
MODE_SACD
DA
T
A_DF
CLK_DF
SIN_DY
XDIS_IO
MLS_RST
AMUT_MCH
MUL
TI
(6/7)
EEPROM
CPU
DATA SELECT
GENERATOR
RESET SIGNAL
5-18. SCHEMATIC DIAGRAM – MAIN Board (6/7) –
•
See page 65 for Waveforms.
•
See page 70 for IC Block Diagrams.
(Page 39)
(Page 41)
(Page 42)
(Page 44)
SCD-XA9000ES
44
44
C913
C940
R857
C914
FB725
FB724
FB726
CN704
CN706
CN705
FB759
FB751
FB761
FB753
FB754
FB755
FB756
R801
R806
R802
R807
C952
IC906
IC810
FL906
CN709
R933
R997
R935
R1000
R986
R985
R911
R993
R994
R995
C918
R999
R923
R922
R909
R908
C907
C917
C911
R931
FL904
R975
C912
IC904
0.1
0.1
220
10
10V
3P
7P
8P
4.7k
10k
4.7k
10k
0.1
TC74VHCT32AFT
SN74AHC1G08DCKR
5P
0
0
10k
0
0
0
1k
0
0
0
0.1
0
10k
10k
10k
10k
0.1
0.1
10
10V
10k
10k
0.1
ISPLSI2032VE
-110LT44
-SA8
F1
F2
H1
H2
H3
I2
I3
I4
I5
I6
I7
I8
I9
D5V
TDO
TDI
BSCAN
TMS
TCK
TMS
TCK
TDO
D0
D1
D2
D3
D4
D5
D6
D7
A0
XRS
T_D
P
XCS_IO
XHWR
XHRD
XRST_DSD
BSCAN
TDI
XRST_DVD
XDIS_IO
VMOD
XRST_CD
AMUTE
BUSY_DP
SIN_DP
SOUT_DP
REQ_DP
SCK_DP
XRST_DP
SDEN
LIM
_SW
TXD
RXD
DGND
5V-D
RXD
TXD
10V-PWE
GND
D/O
3.3VD
GND
(7/7)
NC
NC
LEVEL SHIFT
ON/OFF SWITCH
DIGITAL OUT
I/O EXPANDER
ACK
REQ
SIN
SOUT
SCK
RESET
5-19. SCHEMATIC DIAGRAM – MAIN Board (7/7) –
(Page 43)
(Page 39)
(Page 41)
(Page 42)
(Page 45)
(Page 60)
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