Sony SCD-XA777ES Service Manual ▷ View online
81
SCD-XA777ES
Pin No.
Pin Name
I/O
Description
170
XTA1
I
System clock input terminal (33.8688 MHz)
171
VDD
—
Power supply terminal (+3.3V) (digital system)
172 to 176
D0 to D4
I/O
Two-way data bus with the CPU (IC901) and I/O expander (IC902)
82
SCD-XA777ES
•
MAIN BOARD IC801 CXD2752R (DSD DECODER)
Pin No.
Pin Name
I/O
Description
1
VSCA0
—
Ground terminal (for core)
2
XMSLAT
I
Serial data latch pulse signal input from the CPU (IC901)
3
MSCK
I
Serial data transfer clock signal input from the CPU (IC901)
4
MSDATI
I
Serial data input from the CPU (IC901)
5
VDCA0
—
Power supply terminal (+2.5V) (for core)
6
MSDATO
O
Serial data output to the CPU (IC901)
7
MSREADY
O
Ready signal output to the CPU (IC901) “L”: ready
8
XMSDOE
O
Serial data output enable signal output terminal Not used (open)
9
XRST
I
Reset signal input from the I/O expander (IC902) “L”: reset
10
SMUTE
I
Muting on/off signal input from the CPU (IC901) “H”: muting on
11
MCKI
I
Master clock signal (33.8688 MHz) input terminal
12
VSIOA0
—
Ground terminal (for I/O)
13
EXCKO1
O
External clock 1 signal output terminal Not used (open)
14
EXCKO2
O
External clock 2 signal output terminal Not used (open)
15
LRCK
O
L/R sampling clock signal (44.1kHz) output terminal Not used (open)
16
FRAME
O
Frame signal output terminal Not used (open)
17
VDIOA0
—
Power supply terminal (+3.3V) (for I/O)
18 to 21
MNT0 to MNT3
O
Monitor signal output terminal Not used (open)
22 to 25
TESTO
O
Output terminal for the test (normally: open)
26
TCK
I
Clock signal input terminal for the test (normally: fixed at “L”)
27
TDI
I
Input terminal for the test (normally: open)
28
VSCA1
—
Ground terminal (for core)
29
TDO
O
Output terminal for the test (normally: open)
30
TMS
I
Input terminal for the test (normally: open)
31
TRST
I
Reset terminal for the test (normally: fixed at “L”)
32 to 34 TEST1 to TEST3
I
Input terminal for the test (normally: fixed at “L”)
35
VDCA1
—
Power supply terminal (+2.5V) (for core)
36
TESTO
O
Output terminal for the test (normally: open)
37
XBIT
O
Monitor terminal relative to DST Not used (open)
38 to 41
SUPDT0 to
SUPDT3
O
Supplementary data output terminal Not used (open)
42
VSIOA1
—
Ground terminal (for I/O)
43, 44
SUPDT4, SUPDT5
O
Supplementary data output terminal Not used (open)
45
VDIOA1
—
Power supply terminal (+3.3V) (for I/O)
46, 47
SUPDT6, SUPDT7
O
Supplementary data output terminal Not used (open)
48
XSUPAK
O
Supplementary data acknowledge signal output terminal Not used (open)
49
VSCA2
—
Ground terminal (for core)
50
TESTO
O
Output terminal for the test (normally: open)
51, 52
TESTI
I
Input terminal for the test (normally: fixed at “L”)
53
TESTO
O
Output terminal for the test (normally: open)
54
VDCA2
—
Power supply terminal (+2.5V) (for core)
55, 56
TESTO
O
Output terminal for the test (normally: open)
57
BCKASL
I
Input/output selection signal input terminal of bit clock signal (2.8224 MHz) for DSD data output
“L”: input (slave), “H”: output (master) (fixed at “L” in this set)
“L”: input (slave), “H”: output (master) (fixed at “L” in this set)
58
VSDSD0
—
Ground terminal (for DSD data output)
59
BCKAI
I
Bit clock signal (2.8224 MHz) input for DSD data output from the CXD9647R (IC803)
83
SCD-XA777ES
Pin No.
Pin Name
I/O
Description
60
BCKAO
O
Bit clock signal (2.8224 MHz) output terminal for DSD data output Not used (open)
61
PHREFI
I
Phase reference signal input for DSD output phase modulation from the CXD9647R (IC803)
62
PHREFO
O
Phase reference signal output terminal for DSD output phase modulation Not used (open)
63
ZDFL
O
Zero data (front L-ch) flag detection signal output terminal Not used (open)
64
DSAL
O
DSD data (front L-ch) output to the CXD9647R (IC803)
65
ZDFR
O
Zero data (front R-ch) flag detection signal output terminal Not used (open)
66
DSAR
O
DSD data (front R-ch) output to the CXD9647R (IC803)
67
VDDSD0
—
Power supply terminal (+3.3V) (For DSD data output)
68
ZDFC
O
Zero data (center) flag detection signal output terminal Not used (open)
69
DSAC
O
DSD data (center) output to the CXD9647R (IC803)
70
ZDFLFE
O
Zero data (sub woofer) flag detection signal output terminal Not used (open)
71
DSALFE
O
DSD data (sub woofer) output to the CXD9647R (IC803)
72
VSDSD1
—
Ground terminal (For DSD data output)
73
ZDFLS
O
Zero data (surround L-ch) flag detection signal output terminal Not used (open)
74
DSALS
O
DSD data (surround L-ch) output to the CXD9647R (IC803)
75
ZDFRS
O
Zero data (surround R-ch) flag detection signal output terminal Not used (open)
76
DSARS
O
DSD data (surround R-ch) output to the CXD9647R (IC803)
77
VDDSD1
—
Power supply terminal (+3.3V) (For DSD data output)
78, 79
TESTO
O
Output terminal for the test (normally: open)
80
VSCB0
—
Ground terminal (for core)
81, 82
TESTO
O
Output terminal for the test (normally: open)
83
VDCB0
—
Power supply terminal (+2.5V) (for core)
84, 85
TESTO
O
Output terminal for the test (normally: open)
86
VSIOB0
—
Ground terminal (for I/O)
87
TESTO
O
Output terminal for the test (normally: open)
88, 89
TESTI
I
Input terminal for the test (normally: fixed at “L”)
90
VDIO
—
Power supply terminal (+3.3V) (for I/O)
91 to 93
TESTO
O
Output terminal for the test (normally: open)
94
VSCB1
—
Ground terminal (for core)
95 to 97
TESTI
I
Input terminal for the test (normally: fixed at “L”)
98
TESTO
O
Output terminal for the test (normally: open)
99
VDCB1
—
Power supply terminal (+2.5V) (for core)
100 to 105
TESTI
I
Input terminal for the test (normally: fixed at “L”)
106
VSIOB1
—
Ground terminal (for I/O)
107 to 109
TESTI
I
Input terminal for the test (normally: fixed at “L”)
110
VDIOB1
—
Power supply terminal (+3.3V) (for I/O)
111 to 114 WAD0 to WAD3
I
External A/D data input terminal from the A/D converter for PSP physical disc mark detection
Not used (open)
Not used (open)
115
TESTI
I
Input terminal for disc inspection mode from the I/O expander (IC902)
116
VSCB2
—
Ground terminal (for core)
117 to 120 WAD4 to WAD7
I
External A/D data input terminal from the A/D converter for PSP physical disc mark detection
Not used (open)
Not used (open)
121
VDCB2
—
Power supply terminal (+2.5V) (for core)
122
TESTI
I
Input terminal for the test (normally: fixed at “L”)
123
WCK
I
Operation clock signal input for PSP physical disc mark detection from the CXD1882R (IC701)
124, 125
WAVDD0, 1
—
A/D power supply terminal (+2.5V) (for PSP physical disc mark detection)
84
SCD-XA777ES
Pin No.
Pin Name
I/O
Description
126
WARFI
I
Analog RF signal input for PSP physical disc mark detection from the CXD1881R (IC001)
127
WAVRB
I
A/D bottom reference terminal for PSP physical disc mark detection
128, 129
WAVSS1,0
—
A/D ground terminal (for PSP physical disc mark detection)
130
VSIOA2
—
Ground terminal (for I/O)
131 to 134
DQ7 to DQ4
I/O
Two-way data bus with the D-RAM (IC808)
135
VDIOA2
—
Power supply terminal (+3.3V) (for I/O)
136 to 139
DQ3 to DQ0
I/O
Two-way data bus with the D-RAM (IC808)
140
VSIOA3
—
Ground terminal (for I/O)
141
DCLK
O
Clock signal output to the D-RAM (IC808)
142
DCKE
O
Clock enable signal output to the D-RAM (IC808)
143
XWE
O
Write enable signal output to the D-RAM (IC808)
144
XCAS
O
Column address strobe signal output to the D-RAM (IC808)
145
XRAS
O
Row address strobe signal output to the D-RAM (IC808)
146
VDIOA3
—
Power supply terminal (+3.3V) (for I/O)
147
TESTO
O
Output terminal for the test (normally: open)
148, 149
A11, A10
O
Address signal output to the D-RAM (IC808)
150
VSCA3
—
Ground terminal (for core)
151, 152
A9, A8
O
Address signal output to the D-RAM (IC808)
153
VDCA3
—
Power supply terminal (+2.5V) (for core)
154 to 157
A7 to A4
O
Address signal output to the D-RAM (IC808)
158
VSIOA4
—
Ground terminal (for I/O)
159 to 162
A3 to A0
O
Address signal output to the D-RAM (IC808)
163
VDIOA4
—
Power supply terminal (+3.3V) (for I/O)
164
XSRQ
O
Serial data request signal output to the CXD1882R (IC701)
165
XSHD
I
Header flag signal input from the CXD1882R (IC701)
166
SDCK
I
Serial data transfer clock signal input from the CXD1882R (IC701)
167
XSAK
I
Serial data effect flag signal input from the CXD1882R (IC701)
168
SDEF
I
Error flag signal input from the CXD1882R (IC701)
169 to 176
SD0 to SD7
I
Stream data signal input from the CXD1882R (IC701)
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