Sony SCD-XA777ES Service Manual ▷ View online
77
SCD-XA777ES
Pin No.
Pin Name
I/O
Description
45
AVSS0
—
Ground terminal (analog system)
46
IGEN
I
Stabilized current input for operational amplifiers
47
AVDD0
—
Power supply terminal (+3.3V) (analog system)
48
ASYO
O
Playback EFM full-swing output terminal
49
ASYI
I
Playback EFM asymmetry comparator voltage input terminal
50
RFAC
I
EFM RF signal (AC level) input from the CXD1881R (IC001)
51
AVSS1
—
Ground terminal (analog system)
52
CLTV
I
Internal VCO control voltage input of the EFM playback master PLL
53
FILO
O
Filter output for master clock of the playback EFM master PLL
54
FILI
I
Filter input for master clock of the playback EFM master PLL
55
PCO
O
Phase comparison output for master clock of the playback EFM master PLL
56
AVDD1
—
Power supply terminal (+3.3V) (analog system)
57
BIAS
I
Playback EFM asymmetry circuit constant current input terminal
58
VCTL
I
Control voltage input terminal for the variable pitch Not used (fixed at “L”)
59
V16M
O
16.9344 MHz clock signal output Not used (open)
60
VPCO
O
PLL charge pump output terminal for the variable pitch Not used (fixed at “L”)
61
DVDD2
—
Power supply terminal (+3.3V) (digital system)
62
ASYE
I
Playback EFM asymmetry circuit on/off selection signal input terminal
Not used (fixed at “H”)
Not used (fixed at “H”)
63
MD2
I
Digital out on/off control signal input from the CPU (IC901)
“L”: digital out on, “H”: digital out off
“L”: digital out on, “H”: digital out off
64
DOUT
O
Digital audio signal output to the DIGITAL (CD) OUT OPTICAL (IC442)
65
LRCK
O
L/R sampling clock signal (44.1 kHz) output to the digital filter (IC101, 201, 1101, 1201, 2101,
2201), SACD decoder (IC701), and CXD9647R (IC803)
2201), SACD decoder (IC701), and CXD9647R (IC803)
66
PCMD
O
Serial data output to the digital filter (IC101, 201, 1101, 1201, 2101, 2201), SACD decoder
(IC701), and CXD9647R (IC803)
(IC701), and CXD9647R (IC803)
67
BCLK
O
Bit clock signal (2.8224 MHz) output to the digital filter (IC101, 201, 1101, 1201, 2101, 2201),
SACD decoder (IC701), and CXD9647R (IC803)
SACD decoder (IC701), and CXD9647R (IC803)
68
EMPH
O
Playback disc output terminal in emphasis mode Not used (open)
69
XTSL
I
Input terminal for the system clock frequency setting Fixed at “H” in this set
70
DVSS2
—
Ground terminal (digital system)
71
XTAI
I
System clock input terminal (33.86688 MHz)
72
XTAO
O
System clock output terminal (33.86688 MHz) Not used (open)
73
SOUT
O
Not used (open)
74
SOCK
O
Not used (open)
75
XOLT
I
Not used (open)
76
SQSO
O
Subcode Q data output to the CPU (IC901)
77
SQCK
I
Subcode Q data reading clock signal input from the CPU (IC901)
78
SCOR
O
Not used (open)
79
SBSO
O
Subcode serial data output to the SACD decoder (IC701)
80
EXCK
I
Subcode serial data reading clock signal input to the SACD decoder (IC701)
78
SCD-XA777ES
•
MAIN BOARD IC701 CXD1882R-1 (SACD DECODER)
Pin No.
Pin Name
I/O
Description
1, 2
D5, D6
I/O
Two-way data bus with the CPU (IC901) and I/O expander (IC902)
3
VSS
—
Ground terminal (digital system)
4
D7
I/O
Two-way data bus with the CPU (IC901) and I/O expander (IC902)
5
A0
I
Address signal input from the CPU (IC901)
6
VDD
—
Power supply terminal (+3.3V) (digital system)
7
A1
I
Address signal input from the CPU (IC901)
8
VDD5V
—
Power supply terminal (+5V)
9 to 14
A2 to A7
I
Address signal input from the CPU (IC901)
15
VSS
—
Ground terminal (digital system)
16
XWAIT
O
Wait signal output terminal Not used (open)
17
XRD
I
Read strobe signal input from the CPU (IC901)
18
XWR
I
Write strobe signal input from the CPU (IC901)
19
XCS
I
Chip select signal input from the CPU (IC901)
20, 21
XINT0, XINT1
O
Interrupt signal output to the CPU (IC901)
22
VDD
—
Power supply terminal (+3.3V) (digital system)
23
XHRS
I
Not used (open)
24
HDB7
O
Stream data signal output to the DSD decoder (IC801)
25
VSS
—
Ground terminal (digital system)
26
HDB8
O
Error flag signal output to the DSD decoder (IC801)
27
HDB6
O
Stream data signal output to the DSD decoder (IC801)
28
VDDS
—
Power supply terminal (+5V) (digital system)
29
HDB9
O
Not used (open)
30
HDB5
O
Stream data signal output to the DSD decoder (IC801)
31
HDBA
O
Not used (open)
32
HDB4
O
Stream data signal output to the DSD decoder (IC801)
33
VSS
—
Ground terminal (digital system)
34
HDBB
O
Not used (open)
35
HDB3
O
Stream data signal output to the DSD decoder (IC801)
36
VDD
—
Power supply terminal (+3.3V) (digital system)
37
HDBC
O
Not used (open)
38
VDDS
—
Power supply terminal (+5V) (digital system)
39
HDB2
O
Stream data signal output to the DSD decoder (IC801)
40
HDBD
O
Not used (open)
41
HDB1
O
Stream data signal output to the DSD decoder (IC801)
42
VSS
—
Ground terminal (digital system)
43
HDBE
O
Not used (open)
44
HDB0
O
Stream data signal output to the DSD decoder (IC801)
45
HDBF
O
Not used (open)
46
XSAK
O
Serial data effect flag signal output to the DSD decoder (IC801)
47
VDDS
—
Power supply terminal (+5V) (digital system)
48
XDCK
O
Serial data transfer clock signal output to the DSD decoder (IC801)
49
XSHD
O
Header flag signal output to the DSD decoder (IC801)
50
VDD
—
Power supply terminal (+3.3V) (digital system)
51
REDY
O
Not used (pull up)
52
VSS
—
Ground terminal (digital system)
53
XHAC
I
Serial data request signal input from the DSD decoder (IC801)
79
SCD-XA777ES
Pin No.
Pin Name
I/O
Description
54
HINT
O
Not used (pull up)
55
XS16
O
Not used (pull up)
56
HA1
I
Not used (fixed at “H” )
57
XPDI
I/O
Not used (pull up)
58
VDDS
—
Power supply terminal (+5V) (digital system)
59, 60
HA0, HA2
I
Not used (fixed at “H” )
61
VSS
—
Ground terminal (digital system)
62, 63
HCS0, HCS1
I
Not used (open)
64
VDD
—
Power supply terminal (+3.3V) (digital system)
65
DASP
I/O
Not used (pull up)
66 to 69
MDB0 to MDB3
I/O
Two-way data bus with the D-RAM (IC706)
70
VSS
—
Ground terminal (digital system)
71
MDB4
I/O
Two-way data bus with the D-RAM (IC706)
72
VDD5V
—
Power supply terminal (+5V)
73 to 75
MDB5 to MDB7
I/O
Two-way data bus with the D-RAM (IC706)
76
XMWR
O
Write enable signal output to the D-RAM (IC706)
77
VDD
—
Power supply terminal (+3.3V) (digital system)
78
XRAS
O
Row address strobe signal output to the D-RAM (IC706)
79, 80
MA0, MA1
O
Address signal output to the D-RAM (IC706)
81
VSS
—
Ground terminal (digital system)
82 to 87
MA2 to MA7
O
Address signal output to the D-RAM (IC706)
88
VDD
—
Power supply terminal (+3.3V) (digital system)
89
MA8
O
Address signal output to the D-RAM (IC706)
90
VSS
—
Ground terminal (digital system)
91
MA9/MNT0
O
Address signal output to the D-RAM (IC706)
92
MA10/MNT1
O
RF data signal output terminal Not used (open)
93
MA11/MNT2
O
Operation clock signal output for PSP physical disc mark detection
Monitor signal output to the CPU (IC901)
Monitor signal output to the CPU (IC901)
94
XMOE
O
Output enable signal output to the D-RAM (IC706)
95
XCAS
O
Column address strobe signal output to the D-RAM (IC706)
96, 97
MDB8, MDB9
I/O
Two-way data bus with the D-RAM (IC706)
98
VSS
—
Ground terminal (digital system)
99
MDBA
I/O
Two-way data bus with the D-RAM (IC706)
100
VDD
—
Power supply terminal (+3.3V) (digital system)
101, 102
MDBB, MDBC
I/O
Two-way data bus with the D-RAM (IC706)
103
VDD5V
—
Power supply terminal (+5V)
104 to 106 MDBD to MDBF
I/O
Two-way data bus with the D-RAM (IC706)
107
GFS
O
Guard frame sync signal output to the CPU (IC901)
108
VSS
—
Ground terminal (digital system)
109
APEO
O
Absolute phase error signal output
110
VDD
—
Power supply terminal (+3.3V) (digital system)
111
DASYO
O
RF binary signal output
112
GNDA5
—
Ground terminal (analog system)
113, 114
ASF1, AFS2
—
Filter connected terminal for selection the constant asymmetry compensation
115
DASYI
I
Analog signal input after integrated from the RF binary signal
116
RFDCC
I
Input terminal for adjusting DC cut high-pass filter for RF signal Not used (open)
117
RFIN
I
RF signal input from the CXD1881R (IC001)
80
SCD-XA777ES
Pin No.
Pin Name
I/O
Description
118, 119 VCCA5, VCCA4
—
Power supply terminal (+3.3V) (analog system)
120
VCOR1
—
VCO oscillating range setting resistor connected terminal
121
VCOIN
I
VCO input terminal
122, 123 GNDA4, GNDA3
—
Ground terminal (analog system)
124
LPF5
O
Signal output from the operation amplifier from PLL loop filter
125
VC1
I
Middle point voltage (+1.65V) input terminal
126, 127
LPF2, LPF1
I
Inverted signal input to the operation amplifier from PLL loop filter
128, 129 VCCA3, VCCA2
—
Power supply terminal (+3.3V) (analog system)
130
PDO
O
Signal output from the charge pump for phase comparator
131
PDHVCC
I
Middle point voltage input terminal for RF PLL
132
FDO
O
Signal output from the charge pump for frequency comparator
133, 134 GNDA2, GNDA1
—
Ground terminal (analog system)
135
SPO
O
Spindle motor (M3) control signal output to the BA5912AFP (IC512)
136
VC2
I
Middle point voltage (+1.65V) input terminal
137
MDIN2
I
Spindle motor (M3) servo drive signal input from the CXD3008Q (IC509)
138
MDIN1
I
MDP input terminal
139
VCCA1
—
Power supply terminal (+3.3V) (analog system)
140
CLVS
O
Control signal output for selection the spindle control filter at CLVS
141
VSS
—
Ground terminal (digital system)
142
MDSOUT
O
Frequency error output terminal of internal CLV circuit
143
VDD
—
Power supply terminal (+3.3V) (digital system)
144
MDPOUT
O
Phase error output terminal of internal CLV circuit
145
DEFECT
I
Defect signal input terminal Not used (fixed at “L” )
146
GSCOR
I
Guard subcode sync (S0+S1) detection signal input from the CXD3008Q (IC509)
147
EXCK
O
Subcode serial data reading clock signal output to the CXD3008Q (IC509)
148
SBIN
I
Subcode serial data input from the CXD3008Q (IC509)
149
VSS
—
Ground terminal (digital system)
150
SCOR
I
Subcode sync (S0+S1) detection signal input from the CXD3008Q (IC509)
151
WFCK
I
Write frame clock signal input from the CXD3008Q (IC509)
152
VDD5V
—
Power supply terminal (+5V)
153
XRCI
I
RAM overflow signal input terminal Not used (fixed at “L” )
154
VDDS
—
Power supply terminal (+5V) (digital system)
155
C2PO
I
C2 pointer signal input from the CXD3008Q (IC509)
156
VDD
—
Power supply terminal (+3.3V) (digital system)
157
DBCK
O
Bit clock signal (2.8224 MHz) output terminal Not used (open)
158
BCLK
I
Bit clock signal (2.8224 MHz) input from the CXD3008Q (IC509)
159
DDAT
O
PCM data output terminal Not used (open)
160
MDAT
I
Serial data input from the CXD3008Q (IC509)
161
VSS
—
Ground terminal (digital system)
162
DLRC
O
L/R sampling clock signal (44.1 kHz) output terminal Not used (open)
163
LRCK
I
L/R sampling clock signal (44.1 kHz) input from the CXD3008Q (IC509)
164
XRST
I
Reset signal input from the I/O expander (IC902) “L”: reset
165
IFS0
I
Interface select signal input terminal Fixed at “L” in this set
166
IFS1
I
Interface select signal input terminal Fixed at “H” in this set
167
XTAL
I
33.8688 MHz clock signal input terminal
168
VSS
—
Ground terminal (digital system)
169
XTA2
O
System clock output terminal (33.8688 MHz)
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