Sony NW-HD5 Service Manual ▷ View online
41
NW-HD5
MAIN BOARD IC7001 CXD1616GH (MULTI INTERFACE)
Pin No.
Pin Name
I/O
Description
1
XTAL
I
Sub system clock input terminal Not used
2
EXTAL
O
Sub system clock output terminal Not used
3
CLK2550A
O
Clock signal (22.5792 MHz) output terminal Not used
4
CLK2550X
O
Clock signal (22.5792 MHz) inversion output terminal Not used
5
XOSCSTP
I
Oscillation stop signal input terminal Not used
6
XRESET
I
Reset signal input from the main system controller
7
EXCLKIN
I
Clock signal (176 kHz) input from the main system controller
8 to 30
A1 to A23
I
Address signal input from the main system controller
31 to 46
D0 to D15
I/O
Two-way data bus with the main system controller and flash memory
47 to 49
XCS1 to XCS3
I
Chip select signal input from the main system controller
50
XRD
I
Read signal input from the main system controller
51
XWR
I
Write signal input from the main system controller
52
XLB
I
Write strobe signal input from the main system controller (lower byte)
53
XUB
I
Write strobe signal input from the main system controller (upper byte)
54
XWAIT
I
Wait signal input from the main system controller
55, 56
NC
-
Not used
57
XINTREQG
O
Interrupt request signal output to the main system controller
58
XINTREQH
O
Interrupt request signal output to the main system controller
59
XINTREQU
O
Interrupt request signal output to the main system controller
60 to 72
SA0 to SA12
O
Address signal output to the SD-RAM
73, 74
BA0, BA1
O
Bank selection address signal output to the SD-RAM
75 to 90
SD0 to SD15
I/O
Two-way data bus with the SD-RAM
91
XSCS
O
Chip select signal output to the SD-RAM
92
XRAS
O
Row address strobe signal output to the SD-RAM
93
XCAS
O
Column address strobe signal output to the SD-RAM
94
XSWE
O
Write enable signal output to the SD-RAM
95
LDQM
O
I/O mask signal output to the SD-RAM (lower byte)
96
UDQM
O
I/O mask signal output to the SD-RAM (upper byte)
97
SDCLK
O
Clock signal output to the SD-RAM
98
SDCKE
O
Clock enable signal output to the SD-RAM
99
UA0
O
Address signal output to the USB controller and liquid crystal display unit
100 to 106
UA1 to UA7
O
Address signal output to the USB controller
107 to 114
UD0 to UD7
I/O
Two-way data bus with the USB controller and liquid crystal display unit
115
XUCS0
O
Chip select signal output to the USB controller
116
XUCS1
O
Chip select signal output to the liquid crystal display unit
117
XURD
O
Read signal output to the USB controller and liquid crystal display unit
118
XUWR
O
Write signal output to the USB controller and liquid crystal display unit
119
XUWAIT
I
Wait signal input from the USB controller
120
XUINTREQ
I
Interrupt request signal input from the USB controller
121 to 123
HA0 to HA2
I
Address signal input from the USB controller
124 to 139
HD0 to HD15
I/O
Two-way data bus with the USB controller and hard disk drive unit
140, 141 XHCS0, XHCS1
O
Chip select signal output to the hard disk drive unit
142
XHIOR
O
Read signal output to the hard disk drive unit
143
XHIOW
O
Write signal output to the hard disk drive unit
42
NW-HD5
Pin No.
Pin Name
I/O
Description
144
HIORDY
I
Wait signal input from the hard disk drive unit
145
XHDMACK
O
DMA acknowledge signal output to the hard disk drive unit
146
HDMARQ
I
DMA request signal input from the hard disk drive unit
147
HINTREQ
I
Interrupt request signal input from the hard disk drive unit
148
XHRESET
O
Reset signal output to the hard disk drive unit
149
LRCK
O
L/R sampling clock signal output to the sub system controller
150
BCK
O
Bit clock signal output to the sub system controller
151
DATA
O
Transmission data output to the sub system controller
152
XRDE
O
Transmission enabling signal output to the sub system controller
153
FS256
I
Clock signal (11.2896 MHz) input from the main system controller
154
DTCK
I/O
Two-way TSB communication data bus with the remote commander
155
URESET
O
Reset signal output to the USB controller
156
USLEEP
O
Sleep signal output to the USB controller
157
HDD_PWR_CTL
O
Power supply on/off control signal output terminal for hard disk drive unit
158
GSEN_PWR_CTL
O
Power supply on/off control signal output terminal for acceleration sensor
159
BACKLIT_PWR
O
Power supply on/off control signal output terminal for liquid crystal display back light
160
D33_MODE
O
Power supply on/off control signal output terminal Not used
161
RESET_LCD
O
Reset signal output to the liquid crystal display unit
162
SUSPEND
O
Chip enable signal output to the charge control "L": suspend state
163
VBUS_LIM
O
USB port charge current setting siganal output terminal to the charge control
"H": 500 mA, "L": 100 mA
"H": 500 mA, "L": 100 mA
164
SYNCMODE
I
Sync/non-sync mode selection signal input terminal Not used
165
TDI
I
Data input terminal (for JTAG) Not used
166
TMS
I
Test mode control signal input terminal (for JTAG) Not used
167
TCK
I
Clock signal input terminal (for JTAG) Not used
168
TRST
I
Reset signal input terminal (for JTAG) Not used
169
TDO
O
Data output terminal (for JTAG) Not used
170 to 172 TEST0 to TEST2
I
Input terminal for the test mode setting
173
XICKSTP
I
Sleep signal input from the main system controller
174
NC
-
Not used
175 to 190
VDE33
-
Power supply terminal (+1.2V)
191 to 200
VDE33
-
Power supply terminal (+1.9V)
201 to 206
VDE33
-
Power supply terminal (+3.3V)
207 to 223
GND
-
Ground terminal
224 to 228
NC
-
Not used
43
NW-HD5
MAIN BOARD IC9002 SN412005RHLR (CHARGE CONTROL)
Pin No.
Pin Name
I/O
Description
1
LDO
O
3.3V LDO regurated power supply output terminal
2
ISTAT1
O
Charge progress signal output to the system controller "L": charge state
3
ISTAT2
O
Charge completion signal output to the system controller
4
AC
I
Charge volatage input from the AC adaptor
5, 6
BAT
I/O
Power supply volatage input from the rechargeable battery or charge volatage output to the
rechargeable battery
rechargeable battery
7
ISET2
I
USB port charge current setting siganal input from the multi interface
"H": 500 mA, "L": 100 mA
"H": 500 mA, "L": 100 mA
8
PSEL
I
Charge source selection siganal input terminal "H": AC, "L": USB
9
CE
I
Chip enable signal input input from the multi interface "L": suspend state
10
ISET1
I
Setting terminal for AC input charge current and AC/USB precharge/termination
11
VSS
-
Ground terminal
12
TS
I
Thermal detection signal input terminal
13
DPPM
I
Setting terminal for the dinamic power pass management
14
TMR
I/O
Timer program input terminal Becomes impossible to do safety timer and charge termination
when connecting 1 pin
when connecting 1 pin
15 to 17
OUT
O
Power supply volatage output terminal
18
XACPG
O
AC power good-state detection signal output terminal
19
XUSBPG
O
USB power good-state detection signal output terminal
20
USB
I
Charge volatage input from the USB connector
44
NW-HD5
SECTION 6
EXPLODED VIEWS
Ref. No.
Part No.
Description
Remark
Ref. No.
Part No.
Description
Remark
1
X-2059-961-1 CAP (JACK) S SUB ASSY (for SILVER, RED)
1
X-2059-962-1 CAP (JACK) B SUB ASSY (for BLACK)
2
2-594-374-01 KNOB (HOLD) (for SILVER, RED)
2
2-594-374-11 KNOB (HOLD) (for BLACK)
3
2-594-360-01 CABINET (UPPER) (for SILVER, RED)
3
2-594-360-11 CABINET (UPPER) (for BLACK)
4
2-594-383-01 REINFORCEMENT (JACK)
6
2-594-497-01 BRACKET (STRAP) (for SILVER, RED)
6
2-594-497-11 BRACKET (STRAP) (for BLACK)
7
X-2059-928-2 CABINET (MAIN) S SUB ASSY (SILVER)
7
X-2059-929-2 CABINET (MAIN) R SUB ASSY (RED)
7
X-2059-930-2 CABINET (MAIN) B SUB ASSY (BLACK)
8
3-234-449-25 SCREW (M1.4) (for BLACK, RED)
8
3-234-449-27 SCREW (M1.4) (for SILVER)
9
2-594-367-01 LID, BATTERY CASE (for SILVER)
9
2-594-367-11 LID, BATTERY CASE (for BLACK)
9
2-594-367-21 LID, BATTERY CASE (for RED)
10
3-234-449-11 SCREW (M1.4)
11
X-2059-912-1 LITHIUM ION BATTERY ASSY (US)
11
X-2059-913-1 LITHIUM ION BATTERY ASSY (EXCEPT US)
12
3-234-449-17 SCREW (M1.4) (for BLACK)
12
3-234-449-19 SCREW (M1.4) (for SILVER, RED)
13
3-225-996-02 SCREW (M1.4) (EG), PRECISION PAN
14
3-234-449-31 SCREW (M1.4)
15
2-109-023-01 SHEET (PWB RIB)
16
2-636-102-01 SHEET (REINFORCEMENT JACK)
17
2-635-547-01 SHEET (JACK TERMINAL)
18
X-2102-911-1 BUTTON (TOP) S SUB ASSY (for SILVER)
18
X-2102-956-1 BUTTON (TOP) R SUB ASSY (for RED)
18
X-2102-957-1 BUTTON (TOP) B SUB ASSY (for BLACK)
6-1.
OVERALL SECTION
•
Items marked “*” are not stocked since they
are seldom required for routine service. Some
delay should be anticipated when ordering
these items.
are seldom required for routine service. Some
delay should be anticipated when ordering
these items.
•
The mechanical parts with no reference
number in the exploded views are not supplied.
number in the exploded views are not supplied.
•
Accessories are given in the last of the
electrical parts list.
electrical parts list.
NOTE:
•
-XX and -X mean standardized parts, so they
may have some difference from the original
one.
may have some difference from the original
one.
•
Color Indication of Appearance Parts
Example:
KNOB, BALANCE (WHITE) . . . (RED)
Example:
KNOB, BALANCE (WHITE) . . . (RED)
↑
↑
Parts Color
Cabinet's Color
1
2
3
4
6
7
8
9
15
10
13
10
14
11
main section
not supplied
12
16
17
18
not supplied
not supplied
not
supplied
supplied
not supplied
•
Abbreviation
AUS : Australian model
CH
AUS : Australian model
CH
: Chinese model
JE
: Tourist model
Ver. 1.4
KR
: Korean model
MX : Mexican model
TW : Taiwan model
TW : Taiwan model
Note: Exchange the HINGE (BT) SUB
ASSY (Ref. No. 60 Page 45) when
you exchange CABINET (MAIN)
SUB ASSY (Ref. No. 7).
you exchange CABINET (MAIN)
SUB ASSY (Ref. No. 7).
Click on the first or last page to see other NW-HD5 service manuals if exist.