Sony NW-HD5 Service Manual ▷ View online
37
NW-HD5
Pin No.
Pin Name
I/O
Description
120
PD2/DPLS
O
Test terminal for debug Not used
121
PD3/DMNS
O
Test terminal for debug Not used
122
PD4/TXDPLS
O
Test terminal for debug Not used
123
PD5/TXDMNS
O
Test terminal for debug Not used
124
PD6/TXENL
O
Test terminal for debug Not used
125
PD7/SUSPEND
O
Test terminal for debug Not used
126
VBUS
I
Not used
127
VDIOUS
-
Power supply terminal (for USB transceiver) Not used
128
UDM
I/O
Not used
129
UDP
I/O
Not used
130
TRON
O
Not used
131
AVSDA
-
Ground terminal (for internal D/A converter)
132
VREFER
O
Reference voltage output terminal (R-ch)
133
AOUTR
O
Analog audio signal output to the headphone amplifier (R-ch)
134
AOUTL
O
Analog audio signal output to the headphone amplifier (L-ch)
135
VREFL
O
Reference voltage output terminal (L-ch)
136
AVDDA
-
Power supply terminal (+2.4V) (for internal D/A converter)
137
XTAL
O
Main system clock output terminal (22.5792 MHz)
138
EXTAL
I
Main system clock input terminal (22.5792 MHz)
139
AVDMO
-
Power supply terminal (+2.4V) (for main system clock oscillator)
140
AVSOSC
-
Ground terminal (for main and sub system clock oscillator)
141
TX
O
Sub system clock output terminal (16 MHz)
142
ETX
I
Sub system clock input terminal (16 MHz)
143
AVDUO
-
Power supply terminal (+2.4V) (for sub system clock oscillator)
144
AVSPLL
-
Ground terminal (for PLL)
145
AVDPLL
-
Power supply terminal (+3.3V) (for PLL analog system)
146
PQ0/PGMTR0
O
Sleep signal output to the power control
147
PQ1/PGMTR1
O
Starting factor clear signal output to the power control
148
PQ2/PGMTR2
I
Charge progress signal input from the charge control "L": charge state
149
PQ3/PGMTR3
I
Charge completion signal input from the charge control
150
PQ4
I
AC adaptor detection signal input terminal "L": AC adaptor in
151
PQ5
O
Sleep signal output to the multi interface
152
PQ6
O
Reset signal output to the sub system controller
153
PQ7
O
Reset signal output to the multi interface
154
DVSS8
-
Ground terminal
155
VDIO7
-
Power supply terminal (+1.9V) (for I/O interface)
156
PR0
O
Battery voltage monitor on/off control signal output terminal
157 to 161
PR1 to PR5
-
Not used
162
PR6
O
Headphone/line selection signal output to the headphone amplifier
163
PR7
O
Muting on/off control signal output to the headphone amplifier
164
DVSS9
-
Ground terminal
165
VDIOMS
-
Power supply terminal (+3.3V) (for memory stick interface) Not used
166
MSDIO
I/O
Two-way data bus with the memory stick interface Not used
167
MSBS
O
Bus state signal output to the memory stick interface Not used
168
MSSCLK
O
Clock signal output to the memory stick interface Not used
38
NW-HD5
Pin No.
Pin Name
I/O
Description
169
MSINS
I
Card detection signal input from the memory stick interface Not used
170
P17
I
HOLD key detection signal input terminal "L": hold
171
P10/DADT
I
Audio data input from the memory stick interface Not used
172
P11/ADDT
I
Audio data input from the sub system controller
173
P12/LRCK
I
L/R sampling clock signal input from the sub system controller
174
P13/BCK
I
Bit clock signal input from the sub system controller
175
P14/FS256
O
Clock signal (11.2896 MHz) output to the multi interface
176
P15/MUTFGL
O
Not used
177
P15/MUTFGR
O
Not used
178
DVDD3
-
Power supply terminal (+1.2V) (for core)
179
DVSS5
-
Ground terminal
180
VDIO5
-
Power supply terminal (+1.9V) (for I/O interface)
181
PJ0/WAIT
I
Wait signal input from the multi interface
182
PJ1/RE
O
Read signal output to the multi interface
183
PJ2/LWR/LB
O
Write strobe signal output to the multi interface (lower byte)
184
PJ3/UWR/UB
O
Write strobe signal output to the multi interface (upper byte)
185
PJ4/WE
O
Write signal output to the multi interface
186
PK0/CS0
O
Chip select signal output to the flash memory
187
GAND_XCS1
O
Chip select signal output to the flash memory Used for the E, Taiwan, Korean, Chinese and
Tourist models
Tourist models
188
PK2/XBOOT
I
Boot mode selection signal input terminal Not used
189
PK3/MS_SIO
I
Boot mode selection signal input terminal Not used
190
PK4
I
Not used
191
PK5/CS5
O
Chip select signal output to the multi interface
192
PK6/CS6
O
Chip select signal output to the multi interface
193
PK7/CS7
O
Chip select signal output to the multi interface
194
DVSS6
-
Ground terminal
195
VDIO6
-
Power supply terminal (+1.9V) (for I/O interface)
196 to 207
PL0/A0 to PL7/A7,
PM0/A8 to PM3/A11
O
Address signal output to the flash memry and mullet interface
208
DVSS6
-
Ground terminal
Ver. 1.3
39
NW-HD5
MAIN BOARD IC2001 1S1R72003BOOA100 (USB CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
R1
I/O
Internal operation setting terminal
2
N.C.
-
Not used
3
AVSS
-
Ground terminal (analog system)
4
AVDD
-
Power supply terminal (+3.3V) (analog system)
5
AVSS
-
Ground terminal (analog system)
6
AVDD
-
Power supply terminal (+3.3V) (analog system)
7
AVSS
-
Ground terminal (analog system)
8
DP
I/O
USB data (+) input/output terminal
9
AVSS
-
Ground terminal (analog system)
10
DM
I/O
USB data (-) input/output terminal
11
AVSS
-
Ground terminal (analog system)
12
AVDD
-
Power supply terminal (+3.3V) (analog system)
13
TSTEN
I
Input terminal for the test mode setting
14
VBUS
I
USB bus detection signal input terminal
15
XRESET
I
Reset signal input from the multi interface
16
XSLEEP
I
Sleep signal input from the multi interface
17 to 24
CA0 to CA7
I
Address signal input from the multi interface
25
VSS
-
Ground terminal (logic system)
26
VDD
-
Power supply terminal (+3.3V) (logic system)
27
XCS
I
Chip select signal input from the multi interface
28
XRD
I
Read signal input from the multi interface
29
XWAIT
O
Wait signal output to the multi interface
30
XWR
I
Write signal input from the multi interface
31
XINT
O
Interrupt request signal output to the multi interface
32 to 35
CD0 to CD3
I/O
Two-way data bus with the multi interface and liquid crystal display unit
36
VSS
-
Ground terminal (logic system)
37 to 40
CD4 to CD7
I/O
Two-way data bus with the multi interface and liquid crystal display unit
41
VDD
-
Power supply terminal (+3.3V) (logic system)
42
ATPGEN
I
Input terminal for the test mode setting
43
SCANEN
I
Input terminal for the test mode setting
44, 45
TPORT0, TPORT1
I/O
Input/output terminal for the test mode setting
46, 47
TIN0, TIN1
I
Input terminal for the test mode setting
48
VSS
-
Ground terminal (logic system)
49
OSCOUT
O
Clock signal output terminal Not used
50
VSS
-
Ground terminal (logic system)
51
VDD
-
Power supply terminal (+3.3V) (logic system)
52
XHRESET
I
Reset signal input terminal Not used
53 to 60 HDD4 to HDD11
I/O
Two-way data bus with the multi interface and hard disk drive unit
61
VSS
-
Ground terminal (logic system)
62 to 69
HDD0 to HDD3,
HDD12 to HDD15
I/O
Two-way data bus with the multi interface and hard disk drive unit
70
VDD
-
Power supply terminal (+3.3V) (logic system)
71
HDMARQ
I
DMA request signal input from the hard disk drive unit
72
XHIOW
O
Write signal output to the hard disk drive unit
73
XHIOR
O
Read signal output to the hard disk drive unit
40
NW-HD5
Pin No.
Pin Name
I/O
Description
74
HIORDY
I
Wait signal input from the hard disk drive unit
75
VSS
-
Ground terminal (logic system)
76
VDD
-
Power supply terminal (+3.3V) (logic system)
77
XHDMACK
O
DMA acknowledge signal output to the hard disk drive unit
78
HINTRQ
I
Interrupt request signal input from the hard disk drive unit
79
HA1
O
Address signal output to the multi interface and hard disk drive unit
80
XHPDIAG
I
Diagnosis sequence compression signal input from the hard disk drive unit
81, 82
HA0, HA2
O
Address signal output to the multi interface and hard disk drive unit
83, 84
HCS0, HCS1
O
Chip select signal output to the hard disk drive unit
85
XHDASP
I
Drive valid signal and slave drive detection signal input from the hard disk drive unit
86
VSS
-
Ground terminal (logic system)
87, 88
CLKSEL0,
CLKSEL1
I
Input terminal for oscillation frequency setting Fixed at 12 MHz in this set
89
VSS
-
Ground terminal (logic system)
90
XVSS
-
Ground terminal (logic system)
91
XVDD
-
Power supply terminal (+3.3V) (logic system)
92
VDD
-
Power supply terminal (+3.3V) (logic system)
93
PVDD
-
Power supply terminal (+3.3V) (for PLL)
94
VDD
-
Power supply terminal (+3.3V) (logic system)
95
PVSS
-
Ground terminal (for PLL)
96 to 98
NC
-
Not used
99
XI
I
Sub system clock input terminal (12MHz)
100
XO
O
Sub system clock output terminal (12MHz)
Click on the first or last page to see other NW-HD5 service manuals if exist.