Sony NW-A3000 Service Manual ▷ View online
45
NW-A3000
MAIN BOARD IC8001 LC4128ZC-75MN132C-U5 (PLD)
Pin No.
Pin Name
I/O
Description
1
GND
-
Ground terminal
2
TDI
I
Data input terminal (for JTAG) Not used
3
VCCIO0
-
Power supply terminal (+3V) (for I/O)
4
EX_MULTI_SCK
O
Serial data transfer clock signal output to the real time clock and power control
5
CRADLE_SCK
O
Serial data transfer clock signal output to the cradle
6
FRES_D28
I/O
Two-way data bus with the USB controller, main system controller, SD-RAM and NOR flash
memory
memory
7
CRADLE_SI
O
Serial data output to the cradle
8
MULTI_SI
O
Serial data output to the main system controller
9
FRES_D29
I/O
Two-way data bus with the USB controller, main system controller, SD-RAM and NOR flash
memory
memory
10
GNDIO0
-
Ground terminal (for I/O)
11
EX_MULTI_SO
O
Serial data output to the D/A converter, power control and EL module
12
LCD_XCS
O
Chip select signal output to the EL module "L" active
13
SCLK1
O
Bit clock signal output to the main system controller
14
CRADLE_CS
O
Chip select signal output to the cradle "H" active
15
LRCK1
O
L/R sampling clock signal output to the main system controller
16
TSB
I/O
Two-way TSB communication data bus with the remote commander
17
VCCIO0
-
Power supply terminal (+3V) (for I/O)
18
DAC_XCS
O
Chip select signal output to the D/A converter "L" active
19
FRES_D30
I/O
Two-way data bus with the USB controller, main system controller, SD-RAM and NOR flash
memory
memory
20
RTC_CE
O
Chip enable signal output to the real time clock "H" active
21
FRES_D31
I/O
Two-way data bus with the USB controller, main system controller, SD-RAM and NOR flash
memory
memory
22
PWR_STRB
O
Chip select signal output to the power control "H" active
23
PWR_SLEEP
O
Standby signal output to the power control "H": standby mode
24
GNDIO0
-
Ground terminal (for I/O)
25
PWR_FFCLR
O
Start factor clear signal output to the power control "H" active
26
BAT_MON_CTL
O
Battery voltage monitor on/off control signal output to the power control
"H": battery voltage monitor on
"H": battery voltage monitor on
27
VBUS_LIM
O
USB current limit control signal output to the power control
"L": 100 mA, "H": 500 mA
"L": 100 mA, "H": 500 mA
28
GPIO8
I/O
Not used
29
GPIO20
O
Not used
30
GPIO9
I/O
Not used
31
VCCIO0
-
Power supply terminal (+3V) (for I/O)
32
TCK
I
Clock signal input terminal (for JTAG) Not used
33
VCC
-
Power supply terminal (+1.8V) (for core)
34
GND
-
Ground terminal
35
KEY_LED2
O
LED drive signal output for key illumination "H": LED on
36
XHDD_PWR_CTL
O
Power on/off control signal output for hard disk drive unit "L": power on
37
XUSLEEP
O
Sleep signal output to the USB controller "L": sleep mode
38
HP_MUTE
O
Muting on/off control signal output to the audio amplifier "H": muting on
39
IIS_CLR
O
IIS CLR control signal output terminal
40
EL_PWR
O
Power on/off control signal output for EL module "H": power on
41
GNDIO0
-
Ground terminal (for I/O)
46
NW-A3000
Pin No.
Pin Name
I/O
Description
42
VCCIO0
-
Power supply terminal (+3V) (for I/O)
43
CRD_MUTE1
O
Headphone/cradle selection signal output for audio output "L": headphone, "H": cradle
44
RESET_TSB
O
TSB reset signal output terminal Not used
45
HP_LINE_SEL
O
Headphone/cradle selection signal output for audio output to the audio amplifier
"L": cradle, "H": headphone
"L": cradle, "H": headphone
46
XGSEN_PWR_CTL
O
Standby signal output to the G-sensor "L": standby mode
47
KEY_LED1
O
LED drive signal output for key illumination "H": LED on
48
D33_MODE
O
+3.3V regulator on/off control signal output terminal Not used
49
LCD_SO
I
Serial data input from the EL module Not used
50
NC
-
Not used
51
VCC
-
Power supply terminal (+1.8V) (for core)
52
NC
-
Not used
53
DC_OUT_CTL
O
Power on/off control signal output for cradle "H": power on
54
AF_DCIN_DET
I
AC adaptor connection detection signal input from the power control
"L": AC adaptor is connected
"L": AC adaptor is connected
55
SPI_CS2
I
Chip select signal input for serial control from the main system controller
56
SUSPEND
O
Power on/off control signal output at suspend mode "H": power on
57
SPI_CS1
I
Chip select signal input for serial control from the main system controller
58
JACK_DET
I
Cradle jack detection signal input terminal "L": cradle jack is detected
59
VCCIO1
-
Power supply terminal (+3V) (for I/O)
60
GNDIO1
-
Ground terminal (for I/O)
61
XCHG_STAT1
I
Charge state signal input terminal
62
GPIO5
I
Not used
63
XCHG_STAT2
I
Charge state signal input from the power control
64
SPI_CS0
I
Chip select signal input for serial control from the main system controller
65
DEN_SCK0
O
Serial data transfer clock signal output to the sub system controller
66
PLD_BEEP
O
Beep signal output to the audio amplifier
67
GND
-
Ground terminal
68
TMS
I
Mode selection signal input terminal (for JTAG)
69
VCCIO1
-
Power supply terminal (+3V) (for I/O)
70
MILTI_SCK
I
Serial data transfer clock signal input from the main system controller
71
CRADLE_SO
I
Serial data input from the cradle
72
TSB_SO
I
TSB serial data input from the main system controller
73
DEN_SO0
I
Serial data input from the sub system controller
74
TSB_RW
I
TSB read/write control signal input from the main system controller
75
NC
-
Not used
76
GNDIO1
-
Ground terminal (for I/O)
77
ADP_DET
I
AC adaptor/USB identification signal input terminal "L": USB, "H": AC adaptor
78
DEN_LRCKI
O
L/R sampling clock signal output to the sub system controller
79
NC
-
Not used
80
DEN_BCKI
O
Bit clock signal output to the sub system controller
81, 82
NC
-
Not used
83
VCCIO1
-
Power supply terminal (+3V) (for I/O)
84
SCLK2
I
Bit clock signal input from the main system controller
85
XRST
I
Reset signal input from the power control "L": reset
86
DEN_XRDE
I
Ready/busy selection signal input from the sub system controller "L": ready, "H": busy
87
DENDE_SERQ
I
Interrupt request signal input from the main system controller
88
WAKEUP_DENDE
I
Wake-up signal input from the main system controller
47
NW-A3000
Pin No.
Pin Name
I/O
Description
89
SDATAO1
I
Audio data input from the main system controller
90
GNDIO1
-
Ground terminal (for I/O)
91
MULTI_SO
I
Serial data input from the main system controller
92
DEN_SI0
O
Serial data output to the sub system controller
93
WAKEUP_DEN
O
Wake-up signal output to the sub system controller
94
DEN_SERQ
O
Interrupt request signal output to the sub system controller
95
DEN_PCMDI
O
Audio data output to the sub system controller
96
XRESET_DEN
O
Reset signal output to the sub system controller "L": reset
97
VCCIO1
-
Power supply terminal (+3V) (for I/O)
98
TDO
O
Data output terminal (for JTAG) Not used
99
VCC
-
Power supply terminal (+1.8V) (for core)
100
GND
-
Ground terminal
101
DEN_BCK0
I
Bit clock signal input from the sub system controller
102
XINT_DEN
I
Interrupt request signal input from the sub system controller
103
DEN_PCMD0
I
Audio data input from the sub system controller
104
DEN_DATA_RDY
I
Ready signal input from the sub system controller
105
DEN_SCS0
I
Chip select signal input from the sub system controller
106
DEN_LRCK0
I
L/R sampling clock signal input from the sub system controller
107
GNDIO1
-
Ground terminal (for I/O)
108
VCCIO1
-
Power supply terminal (+3V) (for I/O)
109
FRES_RXW
I
Read/write control signal input from the main system controller
110
IIS_CLR_IN
I
IIS CLR control signal input terminal
111, 112
FRES_A3,
FRES_A2
I
Address signal input from the main system controller
113
FRES_XOE
I
Read signal input from the main system controller
114
FRES_A1
I
Address signal input from the main system controller
115
FRES_XCS1
I
Chip select signal input from the main system controller
116
FS256
I
11.2896 MHz clock signal input from the main system controller
117
VCC
-
Power supply terminal (+1.8V) (for core)
118
NC
-
Not used
119
SCLK3
O
Bit clock signal output to the main system controller
120
DENDE_SS
O
Interrupt permission signal output to the main system controller
121
DATA_READY
O
Ready signal output to the main system controller
122
SDATAI3
O
Audio data output to the main system controller
123
LRCK3
O
L/R sampling clock signal output to the main system controller
124
XINT_DENDE
O
Interrupt request signal output to the main system controller
125
VCCIO0
-
Power supply terminal (+3V) (for I/O)
126
GNDIO0
-
Ground terminal (for I/O)
127
FRES_D27
I/O
Two-way data bus with the USB controller, main system controller, SD-RAM and NOR flash
memory
memory
128
NC
-
Not used
129
FRES_D26
I/O
Two-way data bus with the USB controller, main system controller, SD-RAM and NOR flash
memory
memory
130
NC
-
Not used
131, 132
FRES_D25,
FRES_D24
I/O
Two-way data bus with the USB controller, main system controller, SD-RAM and NOR flash
memory
memory
48
NW-A3000
MAIN BOARD IC9001 uPD68855F9-Y03-BA2-E2-A (POWER CONTROL, CHARGE CONTROL)
Pin No.
Pin Name
I/O
Description
1
VO1
O
Power supply output terminal (+1.1V)
2
VO2
O
Power supply output terminal (+1.8V)
3, 4
VO3
O
Power supply output terminal (+3.3V)
5
VO4
O
Power supply output terminal (+5V)
6
VO4-2
O
Power supply output terminal Not used
7
DCDC4EN
I
Power on/off control signal input for VO4 "H": power on
8
VCCVO1
-
Power supply terminal (+3.7V) (for VO1)
9
VCCVO2
-
Power supply terminal (+3.7V) (for VO2)
10, 11
VCCVO3
-
Power supply terminal (+3.7V) (for VO3)
12
GNDVO1
-
Ground terminal (for VO1)
13
GNDVO2
-
Ground terminal (for VO2)
14, 15
GNDVO3
-
Ground terminal (for VO3)
16
FB1
I
Feedback terminal (for VO1)
17
FB2
I
Feedback terminal (for VO2)
18
FB3
I
Feedback terminal (for VO3)
19
FB4
I
Feedback terminal (for VO4)
20
A1IN
I
Return capacity input terminal (for VO1)
21
A1OUT
O
Return capacity output terminal (for VO1)
22
A2IN
I
Return capacity input terminal (for VO2)
23
A2OUT
O
Return capacity output terminal (for VO2)
24
A3IN
I
Return capacity input terminal (for VO3)
25
A3OUT
O
Return capacity output terminal (for VO3)
26
LDO1IN
I
Power supply input terminal (+1.8V) (for LDO1)
27
LDO2IN
I
Power supply input terminal (+3.3V) (for LDO2)
28
LDO3IN
I
Power supply input terminal (for LDO3) Not used
29
LDO1
O
Power supply output terminal (+1.3V)
30
LDO2
O
Power supply output terminal (+3V)
31
LDO3
O
Power supply output terminal Not used
32
BG1
O
Power supply (BG1) output terminal (+2.8V)
33
BG1 (VDD)
I
Power supply (BG1) input terminal (+2.8V)
34
BG2
O
Power supply (BG2) output terminal (+1.4V)
35
BG3
O
Power supply (BG3) output terminal (+0.6V)
36
VREF
O
Reference voltage output terminal
37
VSTBY
O
Power supply (VSTBY) output terminal (+3V)
38, 39
VSUS1, VSUS2
O
Suspend output terminal Not used
40
WAKE0
I
Wake trigger input terminal (for set key)
41
WAKE1
I
Wake trigger input terminal (for DC power)
42
WAKE2
I
Wake trigger input terminal (for VBUS)
43, 44
WAKE3, WAKE4
I
Wake trigger input terminal Not used
45
WAKE5
I
Wake trigger input terminal (for remote commander key)
46
WAKE6
I
Wake trigger input terminal Not used
47
CLR
I
Start factor clear signal input from the PLD "H" active
48
STBY
I
Standby signal input from the PLD "H": standby mode
49, 50
XRST1, XRST2
O
Reset signal output terminal Not used
51
XRST3
O
Reset signal output to the D/A converter, main system controller, NOR flash memory and PLD
"L": reset
"L": reset
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