Sony NW-A3000 Service Manual ▷ View online
41
NW-A3000
Pin No.
Pin Name
I/O
Description
75
VSS
-
Ground terminal (logic system)
76
VDD
-
Power supply terminal (+3.3V) (logic system)
77
XHDMACK
O
DMA acknowledge signal output to the hard disk drive unit
78
HINTRQ
I
Interrupt request signal input from the hard disk drive unit
79
HA1
O
Address signal output to the hard disk drive unit
80
XHPDIAG
I
Diagnosis sequence compression signal input from the hard disk drive unit
81, 82
HA0, HA2
O
Address signal output to the hard disk drive unit
83, 84
HCS0, HCS1
O
Chip select signal output to the hard disk drive unit
85
XHDASP
I
Drive valid signal and slave drive detection signal input from the hard disk drive unit
86
VSS
-
Ground terminal (logic system)
87, 88
CLKSEL0,
CLKSEL1
I
Input terminal for oscillation frequency setting Fixed at 12 MHz in this set
89
VSS
-
Ground terminal (logic system)
90
XVSS
-
Ground terminal (logic system)
91
XVDD
-
Power supply terminal (+3.3V) (logic system)
92
VDD
-
Power supply terminal (+3.3V) (logic system)
93
PVDD
-
Power supply terminal (+3.3V) (for PLL)
94
VDD
-
Power supply terminal (+3.3V) (logic system)
95
PVSS
-
Ground terminal (for PLL)
96 to 98
NC
-
Not used
99
XI
I
Sub system clock input terminal (12 MHz)
100
XO
O
Sub system clock output terminal (12 MHz)
42
NW-A3000
MAIN BOARD IC6005 SCF5250 (MAIN SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
DATA16
I/O
Two-way data bus with the SD-RAM and NOR flash memory
2
A23
O
Address signal output to the SD-RAM
3
PAD_VDD
-
Power supply terminal (+3V) (for I/O)
4
A22
O
Address signal output to the SD-RAM
5 to 8
A21 to A18
O
Address signal output to the SD-RAM and NOR flash memory
9
PAD_GND
-
Ground terminal (for I/O)
10
A17
O
Address signal output to the NOR flash memory
11 to 14
A16 to A13
O
Address signal output to the SD-RAM and NOR flash memory
15
PAD_VDD
-
Power supply terminal (+3V) (for I/O)
16, 17
A12, A11
O
Address signal output to the SD-RAM and NOR flash memory
18
CORE_VDD
-
Power supply terminal (+1.1V) (for core)
19
CORE_GND
-
Ground terminal (for core)
20, 21
A10, A9
O
Address signal output to the SD-RAM and NOR flash memory
22 to 25
A8 to A5
O
Address signal output to the USB controller and NOR flash memory
26
PAD_GND
-
Ground terminal (for I/O)
27
A4
O
Address signal output to the USB controller and NOR flash memory
28 to 30
A3 to A1
O
Address signal output to the USB controller, NOR flash memory and PLD
31
CS0
O
Chip select signal output to the NOR flash memory
32
XRW
O
Read/write control signal output to the NOR flash memory, PLD and EL module
33
OSC_PAD_VDD
-
Power supply terminal (+3V) (for OSC)
34
CRIN
I
Main system clock input terminal (22.5792 MHz)
35
CROUT
O
Main system clock output terminal (22.5792 MHz)
36
OSC_PAD_GND
-
Ground terminal (for OSC)
37
PLL_CORE1_VDD
-
Power supply terminal (+1.1V) (for PLL)
38
CORE_VDD
-
Power supply terminal (+1.1V) (for core)
39
CORE_GND
-
Ground terminal (for core)
40
PLL_CORE1_GND
-
Ground terminal (for PLL)
41
OE
O
Read signal output to the NOR flash memory, PLD and EL module
42
IDE_DIOW
O
Write signal output to the USB controller
43
IDE_IOPDY
I
Wait signal input from the USB controller
44
IDE_DIOR
O
Read signal output to the USB controller
45
BUFFENB2
O
BUFFENB signal output terminal Not used
46
GSEN_SEL1
O
G-sensor axis selection signal output terminal
47
TA
I
Access complete signal input terminal Not used
48
WAKEUP
I
Wake-up signal input from the USB controller
49
XRESET_LCD
O
Reset signal output to the EL module "L": reset
50
SPI_CS2
O
Chip select signal output for serial control to the PLD
51
PAD_VDD
-
Power supply terminal (+3V) (for I/O)
52
WAKEUP_DENDE
O
Wake-up signal output to the PLD
53
DENDE_SREQ
O
Request signal output to the PLD
54
DATA_READY
I
Ready signal input from the PLD
55
CS1
O
Chip select signal output to the PLD
56
MULTI_SI
I
Serial data input from the PLD and power control
57
MULTI_SCK
O
Serial data transfer clock signal output to the PLD
58
MULTI_SO
O
Serial data output to the real time clock and PLD
59, 60
SPI_CS1, SPI_CS0
O
Chip select signal output for serial control to the PLD
43
NW-A3000
Pin No.
Pin Name
I/O
Description
61
PAD_GND
-
Ground terminal (for I/O)
62
SCLK1
I
Bit clock signal input from the PLD
63
LRCK1
I
L/R sampling clock signal input from the PLD
64
SDATAO1
O
Audio data output to the PLD
65
TSB_XLT
O
TSB latch signal output terminal Not used
66
TSB_RW
O
TSB read/write control signal output to the PLD
67
LCD_DC
O
Resister selection signal output to the EL module
68
FS256
O
11.2896 MHz clock signal output to the D/A converter and PLD
69
SDATAI3
I
Audio data input from the PLD
70, 71
AD_KEY2,
AD_KEY1
I
Set key input terminal (A/D input)
72
AD_RMCKEY (K1)
I
External key input terminal (A/D input)
73
ADVDD
-
Power supply terminal (+3V) (for A/D converter)
74
AD_GND
-
Ground terminal (for A/D converter)
75
AD_BATT
I
Battery voltage monitor input from the power control
76
AD_CRADLE
I
Cradle detection signal input terminal
77
AD_GSEN_XYZ
I
G-sensor input terminal
78
ADREF
-
Reference voltage terminal (for A/D converter)
79
ADOUT
-
Reference voltage terminal (for A/D converter)
80
LRCK3
I
L/R sampling clock signal input from the PLD
81
SCLK3
I
Bit clock signal input from the PLD
82
RDY_XBUSY
I
Ready/busy selection signal input from the NOR flash memory "L": busy, "H": ready
83
XBATT_DET
I
Battery insert detection signal input terminal Not used
84
XINT_DENDE
I
Interrupt request signal input from the PLD
85
USB _IF_EN
O
USB interface enable signal output terminal Not used
86
XINT_USB
I
Interrupt request signal input from the USB controller
87
XINT_HDD
I
Interrupt request signal input from the hard disk drive Not used
88
GSEN_SEL2
O
G-sensor axis selection signal output terminal
89
CORE_VDD
-
Power supply terminal (+1.1V) (for core)
90
CORE_GND
-
Ground terminal (for core)
91
N/C
I
Not used
92
PAD_VDD
-
Power supply terminal (+3V) (for I/O)
93
TCXD0
O
RS232C output terminal for external monitor Not used
94
RXD0
I
RS232C input terminal for external monitor Not used
95
HOLD_KEY
I
HOLD key input terminal
96
MSINS
I
Memory stick insert detection signal input terminal Not used
97
PAD_GND
-
Ground terminal (for I/O)
98
DENDE_SS
I
Interrupt permission signal input from the PLD
99
XRESET_USB
O
Reset signal output to the USB controller "L": reset
100
PSTCLK
O
PSTCLK output terminal Not used
101
DSO
O
DSO output terminal Not used
102
DSI
I
DSI input terminal Not used
103
(N/U)
I
Not used
104
BKPT
I
BKPT input terminal
105
DSCLK
I
DSCLK input terminal Not used
106
RSTI
I
Reset signal input from the power control "L": reset
107
SCLK2
O
Bit clock signal output to the D/A converter
108
LRCK2
O
L/R sampling clock signal output to the D/A converter
44
NW-A3000
Pin No.
Pin Name
I/O
Description
109
LINOUT
O
Not used
110
LININ
I
Not used
111
CORE_VDD
-
Power supply terminal (+1.1V) (for core)
112
SDATAO2
O
Audio data output to the D/A converter
113
NC
I
Not used
114
Hi-Z
-
Not used
115 to 117 TEST0 to TEST2
I
Input terminal for the test mode setting
118
SDW
O
Write enable signal output to the SD-RAM
119
SDCAS
O
Column address signal output to the SD-RAM
120
PAD_VDD
-
Power supply terminal (+3V) (for I/O)
121
SDRAS
O
Row address signal output to the SD-RAM
122
SDCS0
O
Chip select signal output to the SD-RAM
123
SDLDQ
O
Write mask signal output to the SD-RAM (lower byte)
124
SDUDQ
O
Write mask signal output to the SD-RAM (upper byte)
125
BCLKE
O
Clock enable signal output to the SD-RAM
126
BCLK
O
Clock signal output to the SD-RAM
127, 128
DATA31, DATA30
I/O
Two-way data bus with the USB controller, SD-RAM, NOR flash memory and PLD
129
PAD_GND
-
Ground terminal (for I/O)
130 to 134
DATA29 to DATA25
I/O
Two-way data bus with the USB controller, SD-RAM, NOR flash memory and PLD
135
PAD_VDD
-
Power supply terminal (+3V) (for I/O)
136
DATA24
I/O
Two-way data bus with the USB controller, SD-RAM, NOR flash memory and PLD
137 to 140
DATA23 to DATA20
I/O
Two-way data bus with the SD-RAM and NOR flash memory
141
PAD_GND
-
Ground terminal (for I/O)
142 to 144
DATA19 to DATA17
I/O
Two-way data bus with the SD-RAM and NOR flash memory
145 to 163
PAD_VDD
-
Power supply terminal (+3V) (for I/O)
164 to 189
PAD_GND
-
Ground terminal (for I/O)
190 to 192
CORE_VDD
-
Power supply terminal (+1.1V) (for core)
193
BGA_NC_A1
-
Not used
194
BGA_NC_A14
-
Not used
195
BGA_NC_P1
-
Not used
196
BGA_NC_P14
-
Not used
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