Sony NW-A3000 Service Manual ▷ View online
37
NW-A3000
IC8301
TPS61045DRBR
8 SW
CTRL
5
PGND
6
GND
7
2
VIN
1
L
4
FB
3
DO
RS LATCH
LOGIC
UNDER VOLTAGE
LOCKOUT
BIAS SUPPLY
400 ns MIN
OFF TIME
6
µ
s MAX
ON TIME
GATE
DRIVER
GATE
DRIVER
DIGITAL
INTERFACE
6 BIT D/A
CONVERTER
S
R
+
–
+
–
ERROR COMPARATOR
VREF
CURRENT LIMIT
SOFT
START
CTRL
INPUT
SWITCH
MAIN
SWITCH
IC8302
TPS61041DBVR
1
SW
FB 3
GND 2
5 VIN
4 EN
RS LATCH
LOGIC
UNDER VOLTAGE
LOCKOUT
BIAS SUPPLY
400 ns MIN
OFF TIME
6
µ
s MAX
ON TIME
GATE
DRIVER
S
R
+
–
+
–
ERROR COMPARATOR
VREF
CURRENT LIMIT
SOFT
START
38
NW-A3000
•
IC Pin Function Description
MAIN BOARD IC3101 CXR710160-215GH (SUB SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
LRCK
I
L/R sampling clock signal input from the PLD
2
BCK
I
Bit clock signal input from the PLD
3
VDIOCD0
-
Power supply terminal (+1.8V) (for CD interface and I/O)
4
PCMD
I
Audio data input from the PLD
5
DVDD4
-
Power supply terminal (+1.3V)
6
TEST8
O
Output terminal for the test
7
TEST7
I
Input terminal for the test
8
DVDD0
-
Power supply terminal (+1.3V)
9
DVSS0
-
Ground terminal
10
VDIO0
-
Power supply terminal (+1.8V) (for I/O)
11
VDIOCD1
-
Power supply terminal (+1.8V) (for CD interface and I/O)
12
XRDE
I
Ready/busy selection signal input from the PLD "L": ready, "H": busy
13
BCK0
O
Bit clock signal output to the PLD
14
LRCK0
O
L/R sampling clock signal output to the PLD
15
PCMD0
O
Audio data output to the PLD
16
EVA
I
EVA mode selection signal input terminal
17
KCLK
O
Serial data transfer clock signal output terminal Not used
18
KCS
O
Chip select signal output terminal Not used
19
VDIO01
-
Power supply terminal (+1.8V) (for I/O)
20
KDO
O
Serial data output terminal Not used
21
KDI
I
Serial data input terminal Not used
22
KRB
O
Ready/busy selection signal output terminal Not used
23
DVDD1
-
Power supply terminal (+1.3V)
24
DVSS3
-
Ground terminal
25
AVDPLL
-
Power supply terminal (+3V) (for PLL)
26
AVSPLL
-
Ground terminal (for PLL)
27
AVSOSC
-
Ground terminal (for OSC)
28
AVDMO
-
Power supply terminal (+3V) (for OSC)
29
EXTAL
I
Main system clock input terminal (22.5792 MHz)
30
XTAL
O
Main system clock output terminal (22.5792 MHz)
31
XIN
I
External clock input terminal Not used
32
OSSEL
I
External clock control signal input terminal Not used
33
NRST
I
Reset signal input from the PLD "L": reset
34
PF0
I
Wake-up signal input from the PLD
35
PF1
O
Ready signal output to the PLD
36
PF2
I
Interrupt request signal input from the PLD
37
PF3
O
Interrupt request signal output to the PLD
38
PC0
I
Serial data transfer clock signal input from the PLD
39
VDIOCD2
-
Power supply terminal (+1.8V) (for CD interface and I/O)
40
PC1
O
Serial data output to the PLD
41
PC2
I
Serial data input from the PLD
42
PC3
O
Chip select signal output to the PLD
43
DVDD2
-
Power supply terminal (+1.3V)
44
DVSS2
-
Ground terminal
45 to 48
PE0 to PE3
I/O
Not used
49
VDIO2
-
Power supply terminal (+1.8V) (for I/O)
39
NW-A3000
Pin No.
Pin Name
I/O
Description
50, 51
TEST6, TEST5
O
Output terminal for the test
52 to 55
TEST4 to TEST1
I
Input terminal for the test
56
DVDD3
-
Power supply terminal (+1.3V)
57
DVSS1
-
Ground terminal
58
TEST0
I
Input terminal for the test
59
TCK
I
Clock signal input terminal (for JTAG) Not used
60
TDI
I
Data input terminal (for JTAG) Not used
61
VDIO3
-
Power supply terminal (+1.8V) (for I/O)
62
TMS
I
Mode selection signal input terminal (for JTAG) Not used
63
TDO
O
Data output terminal (for JTAG) Not used
64
NTRST
I
Reset signal input terminal (for JTAG) Not used
40
NW-A3000
MAIN BOARD IC5001 S1R72003BOOA100 (USB CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
R1
I/O
Internal operation setting terminal
2
N.C.
-
Not used
3
AVSS
-
Ground terminal (analog system)
4
AVDD
-
Power supply terminal (+3.3V) (analog system)
5
AVSS
-
Ground terminal (analog system)
6
AVDD
-
Power supply terminal (+3.3V) (analog system)
7
AVSS
-
Ground terminal (analog system)
8
DP
I/O
USB data (+) input/output terminal
9
AVSS
-
Ground terminal (analog system)
10
DM
I/O
USB data (-) input/output terminal
11
AVSS
-
Ground terminal (analog system)
12
AVDD
-
Power supply terminal (+3.3V) (analog system)
13
TSTEN
I
Input terminal for the test mode setting
14
VBUS
I
USB bus detection signal input terminal
15
XRESET
I
Reset signal input from the power control "L": reset
16
XSLEEP
I
Sleep signal input from the PLD "L": sleep mode
17 to 24
CA0 to CA7
I
Address signal input from the main system controller
25
VSS
-
Ground terminal (logic system)
26
VDD
-
Power supply terminal (+3.3V) (logic system)
27
XCS
I
Chip select signal input terminal Not used
28
XRD
I
Read signal input from the main system controller
29
XWAIT
O
Wait signal output to the main system controller
30
XWR
I
Write signal input from the main system controller
31
XINT
O
Interrupt request signal output to the main system controller
32 to 35
CD0 to CD3
I/O
Two-way data bus with the main system controller, SD-RAM, NOR flash memory and PLD
36
VSS
-
Ground terminal (logic system)
37 to 40
CD4 to CD7
I/O
Two-way data bus with the main system controller, SD-RAM, NOR flash memory and PLD
41
VDD
-
Power supply terminal (+3.3V) (logic system)
42
ATPGEN
I
Input terminal for the test mode setting
43
SCANEN
I
Input terminal for the test mode setting
44, 45
TPORT0, TPORT1
I/O
Input/output terminal for the test mode setting
46, 47
TIN0, TIN1
I
Input terminal for the test mode setting
48
VSS
-
Ground terminal (logic system)
49
OSCOUT
O
Clock signal output terminal Not used
50
VSS
-
Ground terminal (logic system)
51
VDD
-
Power supply terminal (+3.3V) (logic system)
52
XHRESET
O
Reset signal output to the hard disk drive unit "L": reset
53 to 60
HDD4 to HDD11
I/O
Two-way data bus with the hard disk drive unit
61
VSS
-
Ground terminal (logic system)
62 to 69
HDD0 to HDD3,
HDD12 to HDD15
I/O
Two-way data bus with the hard disk drive unit
70
VDD
-
Power supply terminal (+3.3V) (logic system)
71
HDMARQ
I
DMA request signal input from the hard disk drive unit
72
XHIOW
O
Write signal output to the hard disk drive unit
73
XHIOR
O
Read signal output to the hard disk drive unit
74
HIORDY
I
Wait signal input from the hard disk drive unit
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