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2-6. Power Control by PLD IC8001
PLD IC8001 performs the power controls shown in Table.2-9 (See Fig.2-4).
Table.2-9 List of Power Controls by PLD IC8001
Terminals
ON
OFF
Remarks
IC8001 Pin-40 [EL PWR]
H
L
The power control signal for Step-up DC-DC CONVERTER IC8301
(H: ON)
(H: ON)
IC8001 Pin-46 [XGSEN_PWR_CTL]
L
H
The power control signal for G-Sensor IC4202 (L: ON)
IC8001 Pin-36 [XHDD_PWR_CTL]
L
H
The power control signal for the HDD driving voltage (L: ON)
1. OEL_VCC voltage (NW-A1000/A1200: 15[V], NW-A3000: 17[V])
When VB voltage is input to pin-2 [VIN] of IC8301, IC8301 starts up. And, when “H” signal is supplied from pin-40 [EL_PWR] of PLD IC8001 to pin-5 [CTRL] of IC8301,
IC8301 starts operation. This circuit operates as follows. The step-up DC-DC converter circuit inside IC8301 controls the duty ratio of the PWM waveform which is output from
pin-8 [SW], with monitoring the voltage input to pin-4 [FB] of IC8301. By the operation, the step-up circuit works, and the OEL_VCC voltage is generated.
2. G-Sensor Circuit
When “L” signal is output from pin-46 [XGSEN_PWR_CTL] of PLD IC8001, G-Sensor IC4202 turns “ON”. Then, the monitoring signals for X, Y and Z-axis are output to
Analog Switch IC6003. Next, Main System Control IC6005 recognizes whether the external shock has been applied to the unit by monitoring the signal which is input to pin-77
[AD_GSEN_XYZ]. IC6005 controls the output of pin-7 [COM] of IC6003 by controlling 2 outputs, pin-46 [GSEN_SEL1] and pin-88 [GSEN_SEL0].
Table.2-10 ANALOG SWITCH IC6003
Input
Output
Remark
Pin-6 [IN1]
Pin-5 [IN2]
Pin-7 [COM]
L
L
OFF
No output
H
L
NO0
Monitoring information for X-axis is output.
L
H
NO1
Monitoring information for Y-axis is output.
H
H
NO2
Monitoring information for Z-axis is output.
3. Power Control for HDD
When “L” signal is output from pin-36 [XHDD_PWR_CTL] of PLD IC8001, Q5001 turns “ON”. Then, 3.3V_HDD voltage is supplied to HDD Drive.
In this model, it does not always supply the driving voltage to HDD drive, to realize the lower power consumption as shown in Fig.2-4. Therefore, PLD IC8001 does not supply
the power on signal to G-SENSOR IC4202 when HDD drive is in the sleep mode.
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Fig.2-4 Power Control by PLD IC8001
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3. Playback Circuit
3-1. Playback Circuit-1
Fig.3-1 shows the playback circuit-1.
= Flow of signals to playback ATRAC or MP3 file =
= Flow of signals to playback ATRAC or MP3 file =
MAIN SYSTEM CONTROLLER IC6005/SD-RAM IC7001
MAIN SYSTEM CONTROLLER IC6005 reads out the encrypted music data from HDD drive through the data bus lines. And SD-RAM IC7001 stores the data. Then,
IC6005 reads out the data stored in SD-RAM IC7001. If the data is MP3 format, it is decrypted within IC6005 to be extracted as MP3 data. Then, IC6005 outputs the data
from pin-64 [SDATA01] to PLD IC8001 in synchronization with the bit clock (BCK, 64fs) that is output from pin-62 [SCLK1] and LRCK signal (fs) output from pin-63
[LRCK1]. If the data is ATRAC format, it is transferred to PLD IC8001 as it is without decryption.
MAIN SYSTEM CONTROLLER IC6005 reads out the encrypted music data from HDD drive through the data bus lines. And SD-RAM IC7001 stores the data. Then,
IC6005 reads out the data stored in SD-RAM IC7001. If the data is MP3 format, it is decrypted within IC6005 to be extracted as MP3 data. Then, IC6005 outputs the data
from pin-64 [SDATA01] to PLD IC8001 in synchronization with the bit clock (BCK, 64fs) that is output from pin-62 [SCLK1] and LRCK signal (fs) output from pin-63
[LRCK1]. If the data is ATRAC format, it is transferred to PLD IC8001 as it is without decryption.
PLD IC8001
PLD IC8001 converts the level of the data to send it to IC3101 as IC6005 is 3.0V drive and IC3101 is 1.8V drive.
After conversion, IC8001 output the data from pin-95 [DEN_PCMI] to SUB SYSTEM CONTROLLER IC3101 in synchronization with the bit clock (BCK, 64fs) output from
pin-80 [DEN_BCKI] and LRCK signal (fs) output from pin-78 [DEN_LRCKI].
SUB SYSTEM CONTROLLER IC3101
When SUB SYSTEM CONTROLLER IC3101 receives ATRAC data transferred from IC8001, the Decryption circuit inside IC3101 decrypts the data to extract as ATRAC
format. Then, ATRAC file or MP3 file is input to each decoder inside IC3101. Then, the decoded data is output from pin-15 [PCMDO] to PLD IC8001 in synchronization
with the bit clock (BCK, 64fs) that is output from pin-13 [BCKO] and LRCK signal (fs) output from pin-14 [LRCKO].
When SUB SYSTEM CONTROLLER IC3101 receives ATRAC data transferred from IC8001, the Decryption circuit inside IC3101 decrypts the data to extract as ATRAC
format. Then, ATRAC file or MP3 file is input to each decoder inside IC3101. Then, the decoded data is output from pin-15 [PCMDO] to PLD IC8001 in synchronization
with the bit clock (BCK, 64fs) that is output from pin-13 [BCKO] and LRCK signal (fs) output from pin-14 [LRCKO].
PLD IC8001
IC8001 converts the level of the data from IC3101 before outputting it from pin-122 [SDATAI3] to MAIN SYSTEM CONTROLLER IC6005 in synchronization with the bit
clock (BCK, 64fs) that is output from pin-119 [SCLK3] and LRCK signal (fs) output from pin-123 [LRCK3].
IC8001 converts the level of the data from IC3101 before outputting it from pin-122 [SDATAI3] to MAIN SYSTEM CONTROLLER IC6005 in synchronization with the bit
clock (BCK, 64fs) that is output from pin-119 [SCLK3] and LRCK signal (fs) output from pin-123 [LRCK3].
MAIN SYSTEM CONTROLLER IC6005
After processing the data transferred from IC8001 with a 6-Band equalizer, MAIN SYSTEM CONTROLLER IC6005 outputs the DA data from pin-112 [SDATA2] to D/A
CONVERTER IC3002 in synchronization with the bit clock (BCK, 64fs) that is output from pin-107 [SCLK2] and LRCK signal (fs) output from pin-108 [LRCK2].
After processing the data transferred from IC8001 with a 6-Band equalizer, MAIN SYSTEM CONTROLLER IC6005 outputs the DA data from pin-112 [SDATA2] to D/A
CONVERTER IC3002 in synchronization with the bit clock (BCK, 64fs) that is output from pin-107 [SCLK2] and LRCK signal (fs) output from pin-108 [LRCK2].
D/A CONVERTER IC3002
IC3002 controls the VOLUME with the inside VOLUME control circuit. Then, the inside D/A CONVERTER converts the data to analog signals. The analog signal for L-ch is
output from pin-9 [VOUTL] and the analog signal for R-ch is output from pin-7 [VOUTR].
IC3002 controls the VOLUME with the inside VOLUME control circuit. Then, the inside D/A CONVERTER converts the data to analog signals. The analog signal for L-ch is
output from pin-9 [VOUTL] and the analog signal for R-ch is output from pin-7 [VOUTR].
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= Flow of signals to playback WMA file =
MAIN SYSTEM CONTROLLER IC6005/SD-RAM IC7001
MAIN SYSTEM CONTROLLER IC6005 reads out the encrypted music data from HDD drive through the data bus lines. And SD-RAM IC7001 stores the data. Then,
IC6005 reads out the data stored in SD-RAM IC7001. The data is decrypted within IC6005 to be extracted as WMA file. Then, the Decoder circuit inside IC6005 decodes
the data. Next, IC6005 processes the data with a 6-Band equalizer and outputs it from pin-112 [SDATA2] to D/A CONVERTER IC3002 in synchronization with the bit clock
(BCK, 64fs) that is output from pin-107 and LRCK signal (fs) output from pin-108 [LRCK2].
MAIN SYSTEM CONTROLLER IC6005 reads out the encrypted music data from HDD drive through the data bus lines. And SD-RAM IC7001 stores the data. Then,
IC6005 reads out the data stored in SD-RAM IC7001. The data is decrypted within IC6005 to be extracted as WMA file. Then, the Decoder circuit inside IC6005 decodes
the data. Next, IC6005 processes the data with a 6-Band equalizer and outputs it from pin-112 [SDATA2] to D/A CONVERTER IC3002 in synchronization with the bit clock
(BCK, 64fs) that is output from pin-107 and LRCK signal (fs) output from pin-108 [LRCK2].
D/A CONVERTER IC3002
IC3002 controls the VOLUME with the inside VOLUME control circuit. Then, the inside D/A CONVERTER converts the data to analog signals. The analog signal for L-ch is
output from pin-9 [VOUTL] and the analog signal for R-ch is output from pin-7 [VOUTR].
= One Point =
The models cannot play any WMA file at the present, but firmware update is planned to be released in December, 2005.
The following format of WMA files will be played back on the unit.
- Windows Media Audio file
- Sampling frequency: 44.1[KHz] only
- Bit rate: 192/160/128/96/64/48[kbps] (CBR/VBR)
- Sampling frequency: 44.1[KHz] only
- Bit rate: 192/160/128/96/64/48[kbps] (CBR/VBR)
Note that the WMA files with copyright protection cannot be imported to Connect Player.
= One Point =
To achieve lower power consumption, the unit uses a ceramic type vibrator, X3101, for SUB SYSTEM CONTROLLER IC3101.
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