Sony MDS-NT1 Service Manual ▷ View online
49
MDS-NT1
IC401
BH6519FS-E2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND
VG
IN4R
IN4F
VM4
OUT4F
PGND4
OUT4R
VM34
OUT3R
PGND3
OUT3F
VM3
IN3F
IN3R
PSB
CAPA
–
CAPA+
IN2R
IN2F
VM2
OUT2F
PGND2
OUT2R
VM12
OUT1R
PGND1
OUT1F
VM1
IN1F
IN1R
V
DD
CHARGE
PUMP.
OSC
INTERFACE
AMP
INTERFACE
AMP
AMP
INTERFACE
PREDRIVE
PREDRIVE
PREDRIVE
PREDRIVE
AMP
INTERFACE
AMP
AMP
AMP
V
DD
PSB
AMP
– MAIN Board –
IC400
MAX1626ESA-TE2
1
2
3
4
+
+
–
REF
ERROR
COMPARATOR
CURRENT-SENSE
COMPARATOR
R1
R3
R2
1.5V
MINIMUM ON-TIME
ONE-SHOT
TRIG
Q
MINIMUM OFF-TIME
ONE-SHOT
TRIG
Q
Q
R
R
S
7
8
+
+
–
–
6
5
OUT
3/5
SHDN
REF
EXT
GND
CS
V+
3
4
5
6
+
–
–
COM
+
–
–
COM
8
1
INTERRUPT
SIGNAL
GENERATOR
RESET
SIGNAL
GENERATOR
2
7
INT
RESET
CD
GND
VCC
NC
NC
NC
R1
R2
R4
R3
IC420
M62016FP-E1
50
MDS-NT1
IC505
CXD9627A-E2
IC451
XC6351A120MR
IC440
M54641L
REG.
CONTROL
INPUT
AMP
INPUT
AMP
POWER
AMP
POWER
AMP
1
VCC
2
OUT2
3
IN1
4
GND
5
REFERENCE
6
IN2
7
OUT1
8
VCC
1
2
OSCILLATOR
CHIP
ENABLE
BUFFER
5
6
P1
N3
N4
N2
4
3
GND
CCE/
C1+
VIN
C1–
VOUT
IC503
BH3541F-E2
8
7
1
2
6
5
3
+
0dB
+
0dB
BIAS
MUTE
4
180k
180k
ROUT
MUTE
RIN
VEE
VCC
LOUT
BIAS
LIN
8
7
6
7
6
5
µ
P
INTERFACE
4
3
2
3
2
1
AUDIO
DATA
INTERFACE
DE-EMPHASIS
CONTROL
CLOCK
DIVIDER
8X
INTERPOLATOR
8X
INTERPOLATOR
∆∑
MODULATOR
∆∑
MODULATOR
SCF
SCF
9
10
11
12
12
13
14
15
16
14
15
16
CDTI
CLK
CSN
PDN
LRCK
SDTI
BICK
BICK
MCLK
AOUTR–
AOUTR+
AOUTR+
AOUTL–
AOUTL+
AOUTL+
VSS
VDD
DZFR
DZFL
VDD
DZFR
DZFL
51
MDS-NT1
6-13.
IC PIN FUNCTION DESCRIPTION
•
BD BOARD IC101 CXA2523AR (RF AMP, FOCUS/TRACKING ERROR AMP)
Pin No.
Pin Name
I/O
Description
1
I
I
I-V converted RF signal I input from the optical pick-up block detector
2
J
I
I-V converted RF signal J input from the optical pick-up block detector
3
VC
O
Middle point voltage (+1.65V) generation output terminal
4 to 9
A to F
I
Signal input from the optical pick-up detector
10
PD
I
Light amount monitor input from the optical pick-up block laser diode
11
APC
O
Laser amplifier output to the automatic power control circuit
12
APCREF
I
Reference voltage input for setting laser power
13
GND
—
Ground terminal
14
TEMPI
I
Connected to the temperature sensor
15
TEMPR
O
Output terminal for a temperature sensor reference voltage
16
SWDT
I
Writing serial data input from the CXD2664R
17
SCLK
I
Serial data transfer clock signal input from the CXD2664R
18
XLAT
I
Serial data latch pulse signal input from the CXD2664R
19
XSTBY
I
Standby signal input terminal “L”: standby (fixed at “H” in this set)
20
F0CNT
I
Center frequency control voltage input terminal of internal circuit (BPF22, BPF3T, EQ) input
terminal
terminal
21
VREF
O
Reference voltage output terminal Not used
22
EQADJ
I
Center frequency setting terminal for the internal circuit (EQ)
23
3TADJ
I
Center frequency setting terminal for the internal circuit (BPF3T)
24
VCC
—
Power supply terminal (+3.3V)
25
WBLADJ
I
Center frequency setting terminal for the internal circuit (BPF22)
26
TE
O
Tracking error signal output terminal
27
CSLED
I
Connected to the external capacitor for low-pass filter of the sled error signal
28
SE
O
Sled error signal output terminal
29
ADFM
O
FM signal output terminal of the ADIP
30
ADIN
I
Receives a ADIP FM signal in AC coupling
31
ADAGC
I
Connected to the external capacitor for ADIP AGC
32
ADFG
O
ADIP duplex signal (22.05 kHz
±
1 kHz) output to the CXD2664R
33
AUX
O
Auxiliary signal (I
3
signal/temperature signal) output to the CXD2664R
34
FE
O
Focus error signal output terminal
35
ABCD
O
Light amount signal (ABCD) output terminal
36
BOTM
O
Light amount signal (RF/ABCD) bottom hold output terminal
37
PEAK
O
Light amount signal (RF/ABCD) peak hold output terminal
38
RF
O
Playback EFM RF signal output terminal
39
RFAGC
I
Connected to the external capacitor for RF auto gain control circuit
40
AGCI
I
Receives a RF signal in AC coupling
41
COMPO
O
User comparator output terminal Not used
42
COMPP
I
User comparator input terminal Not used
43
ADDC
I
Connected to the external capacitor for cutting the low band of the ADIP amplifier
44
OPO
O
User operational amplifier output terminal Not used
45
OPN
I
User operational amplifier inversion input terminal Not used
46
RFO
O
RF signal output terminal
47
MORFI
I
Receives a MO RF signal in AC coupling
48
MORFO
O
MO RF signal output terminal
52
MDS-NT1
•
BD BOARD IC201 CXD2664R
Pin No.
Pin Name
I/O
Description
1
MNT0 (FOK)
O
Focus OK signal output terminal “H” is output when focus is on (“L”: NG) Not used
2
MNT1 (SHCK)
O
Track jump detection signal output to the system controller
3
MNT2 (XBUSY)
O
Busy monitor signal output to the system controller
4
MNT3 (SLOC)
O
Spindle servo lock status monitor signal output terminal Not used
5
VDC0
—
Power supply terminal (+2.5V) (for core)
6
SWDT
I
Writing serial data signal input from the system controller
7
SCLK
I
Serial data transfer clock signal input from the system controller
8
XLAT
I
Serial data latch pulse signal input from the system controller
9
VSC0
—
Ground terminal (for core)
10
SRDT
O
Reading serial data signal output to the system controller
11
SENS
O
Internal status (SENSE) output to the system controller
12
XRST
I
Reset signal input from the system controller “L”: reset
13
SQSY
O
Subcode Q sync (SCOR) output to the system controller
“L” is output every 13.3 msec Almost all, “H” is output
“L” is output every 13.3 msec Almost all, “H” is output
14
DQSY
O
Digital In U-bit CD format subcode Q sync (SCOR) output to the system controller
“L” is output every 13.3 msec Almost all, “H” is output
“L” is output every 13.3 msec Almost all, “H” is output
15
RPWR
I
Laser power selection signal input from the system controller
“L”: playback mode, “H”: recording mode
“L”: playback mode, “H”: recording mode
16
XINT
O
Interrupt status output to the system controller
17
TX
O
Magnetic head on/off signal output to the over write head drive
18
VDIO0
—
Power supply terminal (+3.3V) (for I/O)
19
OSCI
I
System clock signal input terminal Not used
20
OSCO
I
System clock signal (2048Fs=90.3168 MHz) input terminal
21
OSCN
I
Control terminal for inverter and feedback resistor of internal oscillator circuit
“L”: OSCO (pin w;) is output terminal, “H”: OSCO (pin w;) is input terminal
(fixed at “H” in this set)
“L”: OSCO (pin w;) is output terminal, “H”: OSCO (pin w;) is input terminal
(fixed at “H” in this set)
22
VSIO0
—
Ground terminal (for I/O)
23
XTSL
I
Input terminal for the system clock frequency setting
“L”: 180.6336 MHz, “H”: 90.3168 MHz (fixed at “H” in this set)
“L”: 180.6336 MHz, “H”: 90.3168 MHz (fixed at “H” in this set)
24
DIN0
I
Digital audio signal input terminal when recording mode Not used
25
DIN1
I
Digital audio signal input terminal when recording mode
26
DOUT
O
Digital audio signal output terminal when playback mode Not used
27
DATAI
I
Recording data input from the USB interface
28
LRCKI
I
L/R sampling clock signal (44.1 kHz) input from the USB interface
29
XBCKI
I
Bit clock signal (2.8224 MHz) input from the USB interface
30
VDC1
—
Power supply terminal (+2.5V) (for core)
31
VSC1
—
Ground terminal (for core)
32
ADDT
I
Recording data input terminal Not used
33
DADT
O
Playback data output to the D/A converter
34
LRCK
O
L/R sampling clock signal (44.1 kHz) output to the D/A converter
35
XBCK
O
Bit clock signal (2.8224 MHz) output to the D/A converter
36
FS256
O
Clock signal (11.2896 MHz) output to the D/A converter
37
XWE
O
Write enable signal output to the D-RAM “L” active
38
XOE
O
Output enable signal output to the D-RAM “L” active
39
DRVDD0
—
Power supply terminal (+3.3V) (for D-RAM interface)
40
DRVSS0
—
Ground terminal (for D-RAM interface)
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO SIGNAL PROCESSOR, EFM/ACIRC ENCODER/DECODER,
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER)
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER)
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